CC1110Fx / CC1111Fx
procedure for setting up DSM mode should
then be as follows:
written to T1CC1L before the most significant
bits are written to T1CC1H.
1. Suspend timer 1 (T1CTL.MODE=00)
The samples written must be signed 2’s
complement values. The 2 least significant bits
will always be treated as 0, thus the effective
sample size is 14 bits.
2. Clear timer counter by writing any value
to T1CNTL, (CNT=0x0000)
3. Set the sample rate by writing to T1CC0.
4. Set Timer 1 channel 0 compare mode
13.6.9 Timer 1 Registers
(T1CCTL0.MODE=1)
This section describes the following Timer 1
registers:
5. Load first sample if available (or zero if
no
sample
available)
into
•
•
•
•
T1CNTH– Timer 1 Counter High
T1CNTL– Timer 1 Counter Low
T1CTL– Timer 1 Control and Status
T1CC1H:T1CC1L.
6. Set timer operation to modulo mode
(T1CTL.MODE=10)
T1CCTLn
Capture/Compare Control
T1CCnH Timer
–
Timer
1
Channel
n
n
n
7. Configure the DSM by setting the MODE
and CAP fields of the T1CCTL1register.
•
•
–
1
Channel
8. Enable
DSM
mode
Capture/Compare Value High
T1CCnL Timer Channel
Capture/Compare Value Low
(T1CCTL1.CMP=111)
1
On each Timer 1 IRQ or Timer 1 DMA trigger,
write a new sample to the T1CC1H:T1CC1L
registers. The least significant bits must be
The TIMIF register is described in section
13.9.7.
T1CNTH (0xE3) – Timer 1 Counter High
Bit
Name
Reset
R/W
Description
7:0
CNT[15:8]
0x00
R
Timer count high order byte. Contains the high byte of the 16-bit timer
counter buffered at the time T1CNTLis read.
T1CNTL (0xE2) – Timer 1 Counter Low
Bit
Name
Reset
R/W
Description
7:0
CNT[7:0]
0x00
R/W
Timer count low order byte. Contains the low byte of the 16-bit timer counter.
Writing anything to this register results in the counter being cleared to
0x0000.
SWRS033E
Page 121 of 239
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