CC1110Fx / CC1111Fx
DMA Trigger
Number
DMA Trigger
Name
Functional
Unit
Description
22
23
24
25
26
ADC_CH1
ADC_CH2
ADC_CH3
ADC_CH4
ADC_CH5
ADC_CH6
ADC
ADC
ADC
ADC
ADC
ADC
ADC end of conversion (AIN1, single-ended or AIN0 – AIN1, differential).
Sample ready
ADC end of conversion (AIN2, single-ended or AIN2 – AIN3, differential).
Sample ready
ADC end of conversion (AIN3, single-ended or AIN2 – AIN3, differential).
Sample ready
ADC end of conversion (AIN4, single-ended or AIN4 – AIN5, differential).
Sample ready
ADC end of conversion (AIN5, single-ended or AIN4 – AIN5, differential).
Sample ready
ADC end of conversion (AIN6, single-ended or AIN6 – AIN7, differential).
Sample ready
27
28
I2SRX
I2S
I2S RX complete
ADC_CH7
ADC
ADC end of conversion (AIN7, single-ended or AIN6 – AIN7, differential).
Sample ready
I2STX
I2S
I2S TX complete
29
30
ENC_DW
ENC_UP
AES
AES
AES encryption processor requests download input data
AES encryption processor requests upload output data
Table 51: DMA Trigger Sources
Byte
Bit
Field Name
Description
Offset
0
1
2
7:0
7:0
7:0
SRCADDR[15:8]
SRCADDR[7:0]
DESTADDR[15:8]
The DMA channel source address, high byte
The DMA channel source address, low byte
The DMA channel destination address, high byte.
Note that flash memory is not directly writeable.
The DMA channel destination address, low byte.
Note that flash memory is not directly writeable.
3
7:0
DESTADDR[7:0]
SWRS033E
Page 108 of 239
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