CC1110Fx / CC1111Fx
IEN2 (0x9A) – Interrupt Enable 2 Register
Bit
Name
Reset
R/W
Description
7:6
0
R/W
Not used
5
4
3
2
1
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Watchdog timer interrupt enable
WDTIE
0
1
Interrupt disabled
Interrupt enabled
Port 1 interrupt enable
P1IE
0
1
Interrupt disabled
Interrupt enabled
USART1 TX interrupt enable / I2S TX interrupt enable
UTX1IE /
I2STXIE
0
1
Interrupt disabled
Interrupt enabled
USART0 TX interrupt enable
UTX0IE
0
1
Interrupt disabled
Interrupt enabled
Port 2 interrupt enable (Also used for USB interrupt enable on CC1111Fx)
P2IE /
USBIE
0
1
Interrupt disabled
Interrupt enabled
RF general interrupt enable
RFIE
0
1
Interrupt disabled
Interrupt enabled
11.5.2 Interrupt Processing
time depends on the current instruction. The
fastest possible response to an interrupt is
seven instruction cycles. This includes one
machine cycle for detecting the interrupt and
six cycles to perform the LCALL.
When an interrupt occurs, the CPU will vector
to the interrupt vector address shown in Table
39, if this particular interrupt has been
enabled. Once an interrupt service has begun,
it can be interrupted only by a higher priority
interrupt. The interrupt service is terminated by
a RETI (return from interrupt) instruction.
When a RETI is performed, the CPU will return
to the instruction that would have been next
when the interrupt occurred.
Clearing interrupt flags must be done correctly
to ensure that no interrupts are lost or
processed more than once. For pulsed or
edge shaped interrupt sources one should
clear the CPU interrupt flag prior to clearing
the module interrupt flag, if available, for flags
that are not automatically cleared. For level
triggered interrupts (port interrupts) one has to
clear the module interrupt flag prior to clearing
the CPU interrupt flag. When handling
interrupts where the CPU interrupt flag is
cleared by hardware, the software should only
clear the module interrupt flag. The following
interrups are cleared by hardware:
When the interrupt condition occurs, an
interrupt flag bit will be set in one of the CPU
interrupt flag registers and in the peripherals
interrupt flag register, if this is available. These
bits are asserted regardless of whether the
interrupt is enabled or disabled. If the interrupt
is enabled when an interrupt flag is asserted,
then on the next instruction cycle the interrupt
will be acknowledged by hardware forcing an
LCALL to the appropriate vector address.
•
•
•
•
RFTXRX
ADC
•
•
•
•
T1
T2
T3
T4
Interrupt response will require a varying
amount of time depending on the state of the
CPU when the interrupt occurs. If the CPU is
performing an interrupt service with equal or
greater priority, the new interrupt will be
pending until it becomes the interrupt with
highest priority. In other cases, the response
URX0
URX1/I2SRX
One or more module flags can be cleared at
once. However the safest approach is to only
handle one interrupt source each time the
interrupt is triggered, hence clearing only one
SWRS033E
Page 65 of 239
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
