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CC1110FX 参数 Datasheet PDF下载

CC1110FX图片预览
型号: CC1110FX
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗低于1 GHz的射频系统级芯片(SoC )与MCU,存储器,收发器和USB控制器 [Low-power sub-1 GHz RF System-on-Chip (SoC) with MCU, memory, transceiver, and USB controller]
分类和应用: 存储射频控制器
文件页数/大小: 240 页 / 2823 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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CC1110Fx / CC1111Fx  
; Tranmit the following data: 0x02, 0x12, 0x34  
; (Assume that the radio has already been configured, the high speed  
; crystal oscillator is selected as system clock, and CLKCON.CLKSPD=000)  
MOV  
JNB  
CLR  
MOV  
JNB  
CLR  
MOV  
JNB  
CLR  
MOV  
RFST,#03H  
RFTXRXIF,C1  
RFTXRXIF  
RFD,#02H  
RFTXRXIF,C2  
RFTXRXIF  
RFD,#12H  
RFTXRXIF,C3  
RFTXRXIF  
; Start TX with STX command strobe  
; Wait for interrupt flag telling radio is  
; ready to accept data, then write first  
; data byte to radio (packet length = 2)  
; Wait for radio  
;
; Send first byte in payload  
; Wait for radio  
C1:  
C2:  
C3:  
;
RFD,#34H  
; Send second byte in payload  
; Done  
Figure 48: Simple RF Transmit Example  
14.5 Data Rate Programming  
The data rate used when transmitting, or the  
data rate expected in receive is programmed  
Min Data  
Rate  
[kBaud]  
Typical Data  
Rate  
[kBaud]  
Max Data  
Rate  
[kBaud]  
Data rate  
Step Size  
[kBaud]  
by  
the  
MDMCFG3.DRATE_M  
and  
the  
MDMCFG4.DRATE_E configuration registers.  
The data rate is given by the formula below.  
0.8  
3.17  
6.35  
12.7  
25.4  
50.8  
101.6  
203.1  
406.3  
1.2 / 2.4  
4.8  
3.17  
6.35  
12.7  
25.4  
50.8  
101.6  
203.1  
406.3  
500  
0.0062  
0.0124  
0.0248  
0.0496  
0.0992  
0.1984  
0.3967  
0.7935  
1.5869  
256 + DRATE _ M  
2DRATE _ E  
)
9.6  
(
RDATA  
=
fref  
228  
19.6  
38.4  
76.8  
153.6  
250  
The following approach can be used to find  
suitable values for a given data rate:  
RDATA 220  
DRATE _ E = log  
2
fref  
500  
RDATA 228  
DRATE _ M =  
256  
Table 62: Data Rate Step Size  
fref 2DRATE _ E  
See section 13.1.5.2 on page 81 for limitations  
in data rate when using other system clock  
speeds than the default.  
If DRATE_M is rounded to the nearest integer  
and becomes 256, increment DRATE_E and  
use DRATE_M=0.  
The datarate can be set from 1.2 kBaud to 500  
kBaud with the minimum step size as found in  
Table 62.  
14.6 Receiver Channel Filter Bandwidth  
In order to meet different channel width  
requirements, the receiver channel filter is  
programmable. The MDMCFG4.CHANBW_E and  
MDMCFG4.CHANBW_M configuration registers  
control the receiver channel filter bandwidth.  
The following formula gives the relation  
between the register settings and the channel  
filter bandwidth:  
fref  
BWchannel  
=
8(4 + CHANBW_ M )·2CHANBW_ E  
For best performance, the channel filter  
bandwidth should be selected so that the  
signal bandwidth occupies at most 80% of the  
channel filter bandwidth. The channel centre  
tolerance due to crystal accuracy should also  
be subtracted from the signal bandwidth. The  
following example illustrates this:  
SWRS033E  
Page 190 of 239