CC1110Fx / CC1111Fx
Notice that interrupts will also be generated if
the corresponding RXIRQ or TXIRQ flags are
set from software, given that the interrupts are
enabled.
The I2S shares interrupt vector with USART 1,
and the ISR must take this into account if both
modules are used. Refer to section 11.5 on
page 61 for more details about interrupts.
(I2SCFG0.ULAWE=1), only the I2SDATH
register needs to be written.
When each sample is more than 8 bits the low
byte must be written to the I2SDATL register
before the high byte is written to the I2SDATH
register, hence writing the I2SDATH register
indicates the completion of the write operation.
When the I2S is configured to send stereo, i.e.
I2SCFG0.TXMONO is 0, the I2SSTAT.TXLR
flag can be used to determine whether the left-
or right-channel sample is to be written to the
data registers.
13.15.3 I2S DMA Triggers
There are two DMA triggers associated with
the I2S interface, I2SRXand I2STX. The DMA
triggers are activated by RX complete and TX
complete events, i.e. the same events that can
generated the I2S interrupt requests. The DMA
triggers are not masked by the interrupt enable
bits, I2SCFG0.RXIEN and I2SCFG0.TXIEN,
hence a DMA channel can be configured to
use the I2S receive/transmit data registers,
I2SDATH:I2SDATL, as source or destination
address and let RX and TX complete trigger
the DMA.
13.15.6 Reading a Word (RX)
If each sample fits into a single byte or if µ-Law
compression is enabled (I2SCFG0.ULAWC=1),
only the I2SDATH register needs to be read.
When each sample is more than 8 bits the low
byte must be read from the I2SDATL register
before the high byte is being read from the
I2SDATH register, hence reading from the
I2SDATH register indicates the completion of
the read operation.
Notice that the DMA triggers I2SRX and
ADC_CH6 share the same DMA trigger
number (# 27) in the same way as I2STX and
ADC_CH7 share DMA trigger number 28. This
means that I2SRX can not be used together
with ADC_CH6 and I2STX can not be used
together with ADC_CH7. On the CC1111Fx ADC
channels 6 and 7 cannot be used since P0_6
and P0_7 I/O pins are not available.
When the I2S is configured to receive stereo,
i.e.
I2SCFG0.RXMONO
is
0,
the
I2SSTAT.RXLRflag can be used to determine
whether the sample currently in the data
registers is a left- or right-channel sample.
13.15.7 Full vs. Half Duplex
Refer to Table 51 on page 108 for an overview
of the DMA triggers.
The I2S interface supports full duplex and half
duplex operation.
13.15.4 Underflow/Overflow
In full duplex both the RX and TX lines will be
used. Both the I2SCFG0.TXIEN and
I2SCFG0.RXIENinterrupt enable bits must be
set to 1 if interrupts are used and both DMA
triggers I2STX and I2SRX must be used.
If the I2S attempts to read from the internal TX
buffer when it is empty, an underflow condition
occurs. The I2S will then continue to read from
the
data
in
the
TX
buffer,
and
I2SSTAT.TXUNFwill be asserted.
When half duplex is used only one of the RX
and TX lines are typically connected. Only the
appropriate interrupt flag should be set and
only one of the DMA triggers should be used.
If the I2S attempts to write to the internal RX
buffer while it is full, an overflow condition
occurs. The contents of the RX buffer will be
overwritten and the I2SSTAT.RXOVF flag will
be asserted.
13.15.8 Master Mode
The I2S is configured as a master device by
setting I2SCFG0.MASTER to 1. When the
module is in master mode, it drives the SCK
and WS lines.
Thus, when debugging an application,
software may check for underflow/overflow
when an interrupt is generated or when the
application completes. The TXUNF / RXOVF
flags should be cleared in software.
13.15.5 Writing a Word (TX)
When each sample fits into a single byte or µ-
Law compressed samples (always 8 bits) are
written, i.e. µ-Law expansion is enabled
SWRS033E
Page 163 of 239
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