CC1110Fx / CC1111Fx
T1CCTL1 (0xE6) – Timer 1 Channel 1 Capture/Compare Control
Bit
Name
Reset
R/W
Description
7
CPSEL
0
R/W
Timer 1 channel 1 capture select
0
1
Use normal capture input
Use RF event(s) enabled in the RFIMregister to trigger a capture
6
IM
1
R/W
R/W
Channel 1 interrupt mask
0
1
Interrupt disabled
Interrupt enabled
5:3
CMP[2:0]
000
Channel 1 compare mode select. Selects action on output when timer value equals
compare value in T1CC1
000
001
010
011
Set output on compare
Clear output on compare
Toggle output on compare
Set output on compare-up, clear on 0 (clear on compare-down in up/down
mode)
100
Clear output on compare-up, set on 0 (set on compare-down in up/down
mode)
101
110
111
Set when equal to T1CC1, clear when equal to T1CC0
Clear when equal to T1CC1, set when equal to T1CC0
DSM mode enable
2
MODE
0
R/W
R/W
CMP≠ 111
CMP= 111
Select Timer 1 channel 1 capture
or compare mode
Set the DSM speed
0
1
Capture mode
Compare mode
1/8 of timer tick speed
1/2 of timer tick speed
1:0
CAP[1:0]
00
Channel 1 capture mode
select (timer mode)
DSM interpolator and output shaping
configuration (DSM mode)
00
01
10
11
No capture
DSM interpolator and output shaping
enabled
Capture on rising edge
Capture on falling edge
Capture on both edges
DSM interpolator enabled and output
shaping disabled
DSM interpolator disabled and output
shaping enabled
DSM interpolator and output shaping
disabled
T1CC1H (0xDD) – Timer 1 Channel 1 Capture/Compare Value High
Bit
Name
Reset
R/W
Description
7:0
T1CC1[15:8] 0x00
R/W
Timer 1 channel 1 capture/compare value, high order byte
DSM data high order byte (DSM mode)
T1CC1L (0xDC) – Timer 1 Channel 1 Capture/Compare Value Low
Bit
Name
Reset
R/W
Description
7:0
T1CC1[7:0]
0x00
R/W
Timer 1 channel 1 capture/compare value, low order byte
DSM data low order byte. The two least significant bits are not used. (DSM mode)
SWRS033E
Page 124 of 239
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
