CC1110Fx / CC1111Fx
T1CC0
T1CCn
0x0000
0: Set output on compare
1: Clear output on compare
2: Toggle output on compare
3: Set output on compare-up,
clear on compare down
4: Clear output on compare-up,
set on compare-down
5: Set when T1CCn,
clear when T1CC0
6: Clear when T1CCn,
set when T1CC0
T1CCn
T1CC0
T1CCn
T1CCn
T1CC0
T1CCn
Figure 33: Output Modes, Timer Up/Down Mode
the terminal count value event (overflow), and
13.6.6 Timer 1 Interrupts
the three channel compare/capture events,
respectively. These flags will be asserted
regardless off the channel n interrupt mask bit
(T1CCTLn.IM). The CPU interrupt flag,
IRCON.T1IF will only be asserted if one or
more of the channel n interrupt mask bits are
set to 1. An interrupt request is only generated
when the corresponding interrupt mask bit is
set together with IEN1.T1EN. The interrupt
mask bits are T1CCTL0.IM, T1CCTL1.IM,
T1CCTL2.IM, and TIMIF.OVFIM. Note that
enabling an interrupt mask bit will generate a
There is one interrupt vector assigned to the
timer. This is T1 (Interrupt #9, see Table 39).
The following timer events may generate an
interrupt request:
• Counter reaches terminal count value
(overflow) or turns around on zero
• Input capture event
• Output compare event
The
T1CTL.CH0IF,
T1CTL.CH2IF contains the interrupt flags for
register
bits
T1CTL.OVFIF,
T1CTL.CH1IF,
and
SWRS033E
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