CC1110Fx / CC1111Fx
responsibility to avoid configurations where the
order of precedence is not conclusive.
clock) in Table 50. The state of P2SEL is
overridden by the debug interface. Also,
P2DIR.DIRP2_1 and P2DIR.DIRP2_2 is
overridden when the chip changes the
direction to supply the external host with data.
13.4.6.6 I2S
The
I2S
configuration
register
bit
I2SCFG1.IOLOC selects whether to use
alternative 1 or alternative 2 locations.
13.4.9 32.768 kHz XOSC Input
Ports P2_3 and P2_4 are used to connect to
an external 32.768 kHz crystal. These port
pins will be set in analog mode and used by
the 32.768 kHz crystal oscillator when
CLKCON.OSC32K is low, regardless of the
configurations of these pins.
In Table 50, the I2S signals are shown as
follows:
• Continuous Serial Clock (SCK): CK
• Word Select: WS
• Serial Data In: RX
• Serial Data Out: TX
13.4.10 Radio Test Output Signals
The I2S interface will have precedence in
cases where other periherals (exept for the
debug interface) are configured to be on the
same location.
For debug and test purposes, a number of
internal status signals in the radio may be
output on the port pins P1_7 – P1_5. This
debug option is controlled through the RF
registers IOCFG2-IOCFG0(see section 16 for
more details).
13.4.7 ADC
When using the ADC in an application, some
or all of the P0 pins must be configured as
ADC inputs. The port pins are mapped to the
ADC inputs so that P0_7 – P0_0 corresponds
to AIN7 - AIN0. To configure a P0 pin to be
used as an ADC input the corresponding bit in
the ADCCFG register must be set to 1. The
default values in this register select the Port 0
Setting IOCFGx.GDOx_CFG to a value other
than 0 will override the P1SEL_SELP1_7,
P1SEL_SELP1_6,
and
P1SEL_SELP1_5
settings, and the pins will automatically
become outputs. These pins cannot be used
when the I2S interface is enabled.
pins
input/outputs.
as
non-ADC
input
i.e.
digital
13.4.11 I/O Registers
The registers for the IO ports are described in
this section. The registers are:
Note: P0_6 and P0_7 do not exist on
CC1111Fx, hence six input channels are
available (AIN0 – AIN5)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
P0Port 0
P1Port 1
P2Port 2
PERCFGPeripheral Control
ADCCFGADC Input Configuration
P0SELPort 0 Function Select
P1SELPort 1 Function Select
P2SELPort 2 Function Select
P0DIRPort 0 Direction
The settings in the ADCCFG register override
the settings in P0SEL (the register used to
select a pin to be either GPIO or to have a
peripheral function).
The ADC can be configured to use the
general-purpose I/O pin P2_0 as an external
trigger to start conversions. P2_0 must be
configured as a general-purpose I/O in input
mode, when being used for ADC external
trigger.
P1DIRPort 1 Direction
P2DIRPort 2 Direction
P0INPPort 0 Input Mode
P1INPPort 1 Input Mode
P2INPPort 2 Input Mode
P0IFGPort 0 Interrupt Status Flag
P1IFGPort 1 Interrupt Status Flag
P2IFGPort 2 Interrupt Status Flag
PICTLPort Interrupt Control
P1IENPort 1 Interrupt Mask
Refer to section 13.10 on page 141 for a
detailed description on how to use the ADC.
13.4.8 Debug Interface
Ports P2_1 and P2_2 are used for debug data
and clock signals, respectively. These are
shown as DD (debug data) and DC (debug
SWRS033E
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