CC1110Fx / CC1111Fx
Figure 20: Flash Write Using DMA
When performing DMA flash write while
executing code from within flash memory, the
instruction that triggers the first DMA trigger
event FLASH (TRIG[4:0]=10010) must be
aligned on a 2-byte boundary. Figure 21 shows
an example of code that correctly aligns the
instruction for triggering DMA (Note that this
code is IAR specific). The code below is
shown for CC1110Fx, but will also work for
CC1111Fx if the include file is being replaced by
ioCC1111.h
; Write flash and generate FLASH DMA trigger
; Code is executed from flash memory
;
#include “ioCC1110.h”
MODULE flashDmaTrigger.s51
RSEG RCODE (1)
PUBLIC halFlashDmaTrigger
FUNCTION halFlashDmaTrigger, 0203H
halFlashDmaTrigger:
ORL FCTL, #0x02;
RET;
END;
Figure 21: DMA Flash Write Executed from within Flash Memory
been initiated by writing a 1 to FCTL.WRITE
13.3.2.2 CPU Flash Write
(see Figure 23). Failure to do so will clear the
FCTL.BYSY bit. FADDRH:FADDRL will contain
the address of the location where write
operation failed. A new write operation can be
started by setting FCTL.WRITEto 1 again and
write two bytes to FWDATA. If one wants to do
the whole write operation over again and not
just start from where it failed, one has to erase
the page, writing the start address to
FADDRH:FADDRL, and setting FCTL.WRITE
to 1 (see section 13.3.3).
The CPU can also write directly to the flash
when executing program code from RAM using
unified memory space. The CPU writes data to
the Flash Write Data register, FWDATA. The
flash memory is written each time two bytes
have been written to FWDATA, if a write has
been enabled by setting FCTL.WRITE to 1.
The CPU can poll the FCTL.SWBSY status to
determine when the flash is ready for two new
bytes to be written to FWDATA.
The steps required to start a CPU flash write
operation are shown in Figure 22. Note that
code must be run from RAM in unified memory
space.
Note that there exist a timeout period of 40 µs
for writing one flash word to FWDATA, thus
writing two bytes to the FWDATA register has
to end within 40 µs after FCTL.SWBSY went
low and also within 40 µs after a write has
SWRS033E
Page 87 of 239
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