CC1110Fx / CC1111Fx
0xDF45: I2SSTAT – I2S Status Register
Bit
Field Name
Reset
R/W
Description
7
6
5
TXUNF
RXOVF
TXLR
0
0
0
R/W
R/W
R
TX buffer underflow. This bit must be cleared by software
Rx buffer overflow. This bit must be cleared by software
0
1
0
1
Left channel should be placed in transmit buffer
Right channel should be placed in transmit buffer
Left channel currently in receive buffer
4
3
RXLR
0
0
R
Right channel currently in receive buffer
TXIRQ
R/W
1
TX interrupt flag. This bit is cleared by hardware when the I2SDATH register is
written.
H0
0
1
Interrupt not pending
Interrupt pending
2
RXIRQ
0
R/W
1
RX Interrupt flag. This is cleared by hardware when the I2SDATH register is read.
0
1
Interrupt not pending
Interrupt pending
H0
1:0
WCNT[9:8]
00
R
Upper 2 bits of the 10-bit internal word counter at the time of the last trigger
0xDF46: I2SCLKF0 – I2S Clock Configuration Register 0
Bit
Field Name
Reset
R/W
Description
7:0
DENOM[7:0]
0x93
R/W
The clock division denominator low bits
0xDF47: I2SCLKF1 – I2S Clock Configuration Register 1
Bit
Field Name
Reset
R/W
Description
7:0
NUM[7:0]
0xE2
R/W
Clock division numerator low bits
0xDF48: I2SCLKF2 – I2S Clock Configuration Register 2
Bit
Field Name
Reset
R/W
Description
7
DENOM[8]
NUM[14:8]
0
R/W
R/W
Clock division denominator high bits
Clock division numerator high bits
6:0
0x04
SWRS033E
Page 168 of 239
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
