CC1110Fx / CC1111Fx
13.11 Random Number Generator
The random number generator is a 16-bit
Linear Feedback Shift Register (LFSR) with
13.11.1 Introduction
polynomial X 16 + X 15 + X 2 +1 (i.e. CRC16).
It uses different levels of unrolling depending
on the operation it performs. The basic version
(no unrolling) is shown below.
The random number generator has the
following features.
• Generate pseudo-random bytes which
can be read by the CPU.
• Calculate CRC16 of bytes that are
written to RNDH.
The random number generator is turned off
when ADCCON1.RCTRL=11.
• Seeded by value written to RNDL.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
+
+
in_bit
+
Figure 39: Basic Structure of the Random Number Generator
13.11.2 Random Number Generator Operation
13.11.2.3 CRC16
The operation of the random number generator
is controlled by the ADCCON1.RCTRLbits. The
current value of the 16-bit shift register in the
LFSR can be read from the RNDH and RNDL
registers.
The LFSR can also be used to calculate the
CRC value of a sequence of bytes. Writing to
the RNDH register will trigger
a
CRC
calculation. The new byte is processed from
the MSB end and an 8x unrolling is used, so
that a new byte can be written to RNDH every
clock cycle.
13.11.2.1 Semi Random Sequence
Generation
Note that the LFSR must be properly seeded
by writing to RNDL, before the CRC
calculations start. Usually the seed value
should be 0x0000 or 0xFFFF. Using 0xFFFF
as seed value will give the CRC used by the
radio.
The default operation (ADCCON1.RCTRL=00)
is to clock the LSFR once (13x unrolling) thus
give a new pseudo-random byte from LSB of
the LSFR each time the RNDLregister is read.
Another way is to update the LFSR is to set
ADCCON1.RCTRL=01. This will clock the LFSR
once (no unrolling) and the ADCCON1.RCTRL
bits will automatically be cleared when the
operation has completed.
For the following byte sequence:
0x03, 0x41, 0x42, 0x43
The CRC will be 0xB4BC when using 0xFFFF
as seed value.
13.11.2.2 Seeding
13.11.3 Registers
The LFSR can be seeded by writing to the
RNDL register twice. Each time the RNDL
register is written, the 8 LSB of the LFSR is
copied to the 8 MSB and the 8 LSBs are
replaced with the new data byte that was
written to RNDL.
The random number generator registers are
described in this section.
SWRS033E
Page 147 of 239
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