CC1110Fx / CC1111Fx
Parameter
Min
Typ
Max
Unit
Condition
Digital regulator on. High speed crystal oscillator and low power
RCOSC running. Radio in RX mode (sensitivity optimized
MDMCFG2.DEM_DCFILT_OFF=1)
Active mode with
radio in RX,
433 MHz
19.8
19.7
17.1
19.8
19.7
19.8
17.1
19.8
20.5
21.5
18.1
20.5
20.2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1.2 kBaud, input at sensitivity limit, system clock at 26 MHz.
1.2 kBaud, input at sensitivity limit, system clock at 24 MHz.
1.2 kBaud, input at sensitivity limit, system clock at 203 kHz.
1.2 kBaud, input well above sensitivity limit, system clock at 26 MHz.
1.2 kBaud, input well above sensitivity limit, system clock at 24 MHz.
38.4 kBaud, input at sensitivity limit, system clock at 26 MHz.
38.4 kBaud, input at sensitivity limit, system clock at 203 kHz
38.4 kBaud, input well above sensitivity limit, system clock at 26 MHz.
250 kBaud, input at sensitivity limit, system clock at 26 MHz.
250 kBaud, input at sensitivity limit, system clock at 24 MHz.
250 kBaud, input at sensitivity limit, system clock at 1.625 MHz.
250 kBaud, input well above sensitivity limit, system clock at 26 MHz.
250 kBaud, input well above sensitivity limit, system clock at 24 MHz
See Figure 2 for typical variation over operating conditions
Digital regulator on. High speed crystal oscillator and low power
RCOSC running. Radio in RX mode (sensitivity optimized
MDMCFG2.DEM_DCFILT_OFF=1). 24MHz system clock not
measured
Active mode with
radio in RX,
868, 915 MHz
19.7
17.0
18.7
19.7
17.0
18.7
20.4
18.0
19.1
mA
mA
mA
mA
mA
mA
mA
mA
mA
1.2 kBaud, input at sensitivity limit, system clock at 26 MHz.
1.2 kBaud, input at sensitivity limit, system clock at 203 kHz.
1.2 kBaud, input well above sensitivity limit, system clock at 26 MHz.
38.4 kBaud, input at sensitivity limit, system clock at 26 MHz.
38.4 kBaud, input at sensitivity limit, system clock at 203 kHz.
38.4 kBaud, input well above sensitivity limit, system clock at 26 MHz.
250 kBaud, input at sensitivity limit, system clock at 26 MHz.
250 kBaud, input at sensitivity limit, system clock at 1.625 MHz.
250 kBaud, input well above sensitivity limit, system clock at 26 MHz.
System clock running at 26 MHz or 24MHz.
Active mode with
radio in TX,
315 MHz
Digital regulator on. High speed crystal oscillator and low power
RCOSC running. Radio in TX mode
31.5
19
mA
mA
mA
+10 dBm output power (PA_TABLE0=0xC2)
0 dBm output power (PA_TABLE0=0x51)
-6 dBm output power (PA_TABLE0=0x2A)
18
SWRS033E
Page 11 of 239
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