W681308
XXXX PRODUCT DESCRIPTION
10.
10.1
Interrupt Control
Overview
The W681308 generates internal events, these interrupt events are triggered by the interrupt control logic. The MCU
supports two priority levels of interrupts with 6 interrupt sources.
10.2
Functionality
The External Interrupts INT0 and INT1 can be either edge triggered or level triggered,
The Interface and Support logic generate the following interrupts:
NFS interrupt
Keypad-Wakeup Interrupt
GPIO interrupt
SPI interrupt
W2S interrupt
USB interrupt
Three registers control the generation of interrupts in the W681308, the interrupt source register, the interrupt enable register
and the interrupt priority register. Each interrupt has a corresponding bit in these three registers.
The interrupt source register is set when an interrupt event occurs and is cleared by MCU.
When the MCU writes to interrupt source, any bit that is set to 1 cause the corresponding bit of interrupt source to be cleared,
bits set to 0 are not affected (write “one” to clear).
An Interrupt is generated when (interrupt source) & (interrupt enable) =1 for any of the interrupt sources. For each bit; if
interrupt priority = 0, the interrupt is issued to INT0, if interrupt priority = 1, the interrupt is issued to INT1.
Interrupt
Source
&
INT0
&
Interrupt
Enable
INT1
&
Interrupt
Priority
Figure 3 Interrupt Structure
31
Rev1.2
NUVOTEM TALEMA [ NUVOTEM TALEMA ]
