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SM8954BW40PP 参数 Datasheet PDF下载

SM8954BW40PP图片预览
型号: SM8954BW40PP
PDF下载: 下载PDF文件 查看货源
内容描述: SM8954B\n8位微控制器\n16KB闪存\n和1KB RAM的嵌入式 [SM8954B 8-Bit Micro-controller 16KB Flash & 1KB RAM embedded]
分类和应用: 闪存微控制器
文件页数/大小: 49 页 / 1595 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
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SM8954B  
8-Bit Micro-controller  
16KB Flash  
& 1KB RAM embedded  
only)  
RESTART: This bit only set by master mode. The master will send a start signal then send  
TWSIA after the ACK signal when this bit setting. If NAKIF was set (the NACK  
signal was received), the master mode will release, and this bit will clear.  
(Master mode only)  
MRW: This bit is determined the data transmit direction. And this bit will transmit to  
bus as bit0 at Address (Address is collection TWSIA [7:1] and MRW as 8 bits  
data). When clear this bit the master is in transmits mode and clear is in  
receive mode.  
Mnemonic: TWSITXD  
Address: C4h  
7
6
5
4
3
2
1
0
Reset  
TXD.7  
TXD.6  
TXD.5  
TXD.4  
TXD.3  
TXD.2  
TXD.1  
TXD.0  
FFh  
The data written into this register will be automatically downloaded to the shift register when the module detects a  
calling address is matched and the bit 0 of the received data is one (Slave transmit mode) or when the data in the  
shift register has been transmitted with received acknowledge bit (RXAK) =0 in transmit mode.  
Mnemonic: TWSIRXD  
Address: C5h  
7
6
5
4
3
2
1
0
Reset  
RXD.7  
RXD.6  
RXD.5  
RXD.4  
RXD.3  
RXD.2  
RXD.1  
RXD.0  
00h  
The TWSI Receive Data Buffer (TWSIRXD) contains the last received data when the MATCH flag is one or the  
calling address from master when the MATCH flag is zero. The TWSIRXD register will be updated after a data byte  
is received and the previous received data had been read out, otherwise the TWSI module will pull down to SCL  
line to inhabit the next data transfer. It is a read-only register. The read operation of this register will clear the RXIF  
flag. After the RXIF flag is cleared, the register can load the received data again and set the RXIF flag to generate  
interrupt request for reading the newly received data.  
Mnemonic: IFR  
Address: AAh  
7
-
6
-
5
-
4
-
3
-
2
-
1
0
-
Reset  
00h  
TWSIIF  
TWSIIF: It is the logic-ORed result of following TWSI flags : RXIF, TXIF, TFIF and  
NAKIF. Firmware can poll this bit to check whether TWSI’s flag is set. (Read  
only)  
Specifications subject to change without notice contact your sales representatives for the most recent information.  
ISSFD-M083 Ver A SM8954B 3/7/2014  
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