SM8951AC40 参数 Datasheet PDF下载

SyncMOS Technologies International, Inc.

SM8951A/8952A

8-Bits Micro-controller

With 4/8KB flash embedded

Watch Dog Timer Registers - WDT Control Register (WDTC, $9F)

WDTE

Read / Write:

Reset value:

R/W

0

MSB

WDTE : Watch Dog Timer enable bit

CLEAR : Watch Dog Timer reset bit

If CLEAR bit set to 1 , Watch Dog Timer will be reset . User don’t reset value to 0 .

PS2~PS0:clock source divider bit

PS [2:0]

000

001

010

011

100

101

110

111

Divider (OSC in)

8

16

32

64

128

256

512

1024

Time Period (ms) @40MHZ

13.1

26.21

52.42

104.8

209.71

419.43

838.86

1677.72

R

-

*

Clear

-

0

Unused

-

*

Unused

-

*

PS2

R/W

0

PS1

R/W

0

PS0

R/W

0

LSB

Watch Dog Timer Register - System Control Register (SCONF, $BFH)

bit-7

WDR

Read / Write:

Reset value:

R/W

0

Unused

-

*

Unused

-

*

Unused

-

*

Unused

-

*

Unused

-

*

Unused

-

*

bit-0

ALEI

R/W

0

WDR : Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1

ALEI : ALE output inhibit bit, to reduce EMI

The bit 7(WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated

by WDT overflow. User should check WDR bit whenever un-predicted reset happened.

Reduce EMI Function

The SM8951A/8952A allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This

function will inhibit the clock signal in Fosc/6Hz output to the ALE pin. This function is available when there is no

external pro gram memory or no external data RAM in the system.

Specifications subject to change without notice contact your sales representatives for the most recent information.

6

Ver 2.1

SM8951A/8952A 08/2006