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SM89516C25 参数 Datasheet PDF下载

SM89516C25图片预览
型号: SM89516C25
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,具有64KB闪存和1KB RAM的嵌入式 [8-Bits Micro-controller With 64KB flash & 1KB RAM embedded]
分类和应用: 闪存微控制器
文件页数/大小: 19 页 / 735 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
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SyncMOS Technologies International, Inc.  
SM89516  
8-Bits Micro-controller  
With 64KB flash & 1KB RAM embedded  
AC Characteristics  
(16/25MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=100pF; CL for all Other Output=80pF)  
fosc=16MHz  
Min. Typ. Max  
Variable fosc  
Typ. Max  
Symbol  
Parameter  
Valid Cycle  
Unit  
Remarks  
Min.  
T LHLL  
T AVLL  
T LLAX  
T LLIV  
T LLPL  
T PLPH  
T PLIV  
T PXIX  
T PXIZ  
T AVIV  
T PLAZ  
T RLRH  
T WLWH  
T RLDV  
T RHDX  
T RHDZ  
T LLDV  
T AVDV  
T LLYL  
ALE pulse width  
Address Valid to ALE low  
Address Hold after ALE low  
ALE low to Valid Instruction In  
ALE low to #PSEN low  
#PSEN pulse width  
#PSEN low to Valid Instruction In  
Instruction Hold after #PSEN  
Instruction Float after #PSEN  
Address to Valid Instruction In  
#PSEN low to Address Float  
#RD pulse width  
RD/WRT  
RD/WRT  
RD/WRT  
RD  
115  
43  
53  
2xT - 10  
T - 20  
T - 10  
nS  
nS  
nS  
240  
4xT - 10 nS  
RD  
RD  
RD  
RD  
RD  
RD  
RD  
RD  
WRT  
RD  
RD  
RD  
RD  
53  
T - 10  
3xT - 15  
nS  
173  
177  
0
nS  
3xT - 10 nS  
nS  
0
87  
292  
10  
T + 25  
5xT -20  
10  
nS  
nS  
nS  
nS  
nS  
365  
365  
302  
0
6xT - 10  
6xT - 10  
#WR pulse width  
#RD low to Valid Data In  
Data Hold after #RD  
Data Float after #RD  
ALE low to Valid Data In  
Address to Valid Data In  
5xT - 10 nS  
nS  
0
145  
590  
542  
2xT+20  
nS  
8xT - 10 nS  
9xT - 20 nS  
RD  
ALE low to #WR High or #RD low
 
RD/WRT  
178  
230  
403  
38  
197 3xT - 10  
4xT - 20  
7xT - 35  
T - 25  
3xT+10  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
T AVYL Address Valid to #WR or #RD low RD/WRT  
T QVWH  
T QVWX  
T WHQX  
T RLAZ  
T YALH  
T CHCL  
T CLCX  
T CLCH  
T CHCX  
T, TCLCL  
Data Valid to #WR High  
Data Valid to #WR transition  
Data hold after #WR  
#RD low to Address Float  
#WR or #RD high to ALE high  
clock fall time  
WRT  
WRT  
WRT  
RD  
RD/WRT  
73  
T + 10  
5
53  
72  
T -10  
T + 10  
clock low time  
clock rise time  
clock high time  
clock period  
63  
1/fosc  
Specifications subject to change without notice contact your sales representatives for the most recent information.  
Ver 2.1 SM89516 08/2006  
11