SyncMOS Technologies International, Inc.
SM89516A
8-Bits Micro-controller
With 64KB flash & 1KB RAM embedded
Watch Dog Key Register - (WDTKEY, $97H)
bit-7
bit-0
WDT
KEY7
W
WDT
KEY6
W
WDT
KEY5
W
WDT
KEY4
W
WDT
KEY3
W
WDT
KEY2
W
WDT
KEY1
W
WDT
KEY0
W
Read / Write:
Reset value:
0
0
0
0
0
0
0
0
By default, the WDTC is read only. User need to write values 1EH, E1H sequentially to the WDTKEY($97H) register to
enable the WDTC write attribute, That is
MOV WDTKEY, # 1EH
MOV WDTKEY, # E1H
When WDTC is set, user need to write another values E1H, 1EH sequentially to the WDTKEY($97H) register to
disable the WDTC write attribute, That is
MOV WDTKEY, # E1H
MOV WDTKEY, # 1EH
Watch Dog Timer Register - System Control Register (SCONF, $BF)
bit-7
bit-0
WDR
R/W
0
Unused
Unused
Unused
Unused
Unused
OME
R/W
0
ALEI
R/W
0
Read / Write:
Reset value:
-
*
-
*
-
*
-
*
-
*
The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT
overflow. User should check WDR bit whenever un-predicted reset happened
4. Reduce EMI Function
The SM89516A allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This
function will inhibit the clock signal in Fosc/6Hz output to the ALE pin.
5. Specific Pulse Width Modulation (SPWM)
The Specific Pulse Width Modulation (SPWM) module contain 1 kind of PWM sub module: SPWM (Specific PWM).
SPWM has five 8-bit channels.
5.1 SPWM Function Description:
The 8-bit SPWM channel is composed of an 8-bit register which contains a 5-bit SPWM in MSB portion and a 3-bit
binary rate multiplier (BRM) in LSB portion. The value programmed in the 5-bit SPWM portion will determine the pulse
length of the output. The 3-bit BRM portion will generate and insert certain narrow pulses among an 8-SPWM-cycle
frame. The number of pulses generated is equal to the number programmed in the 3-bit BRM portion. The usage of the
BRM is to generate equivalent 8-bit resolution SPWM type DAC with reasonably high repetition rate through 5-bit
SPWM clock speed. The SPFS[1:0] settings of SPWMC ($A3) register are dividend of Fosc to be SPWM clock,
Fosc/2^(SPFS[1:0]+1). The SPWM output cycle frame repetition rate (frequency) equals (SPWM clock)/32 which is
[Fosc/2^(SPFS[1:0]+1)]/32.
Specifications subject to change without notice contact your sales representatives for the most recent information.
Ver 2.1 SM89516A 08/2006
10
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
