SyncMOS Technologies International, Inc.
SM894051
8-Bits Micro-controller
With 4KB Flash ROM embedded
ORL
ORL
MOV
MOV
JC
JNC
JB
JNB
JBC
C,bit
C,/bit
C,bit
bit,C
rel
C = C .OR. bit
C = C .OR. /bit
C = bit
2
2
2
2
2
2
3
3
3
2
2
1
2
2
2
2
2
2
bit = C
Jump if C= 1
Jump if C= 0
Jump if bit = 1
Jump if bit = 0
Jump if C = 1
rel
bit,rel
bit,rel
bit,rel
Jump Instructions
ACALL
LCALL
RET
RETI
AJMP
LJMP
SJMP
JMP
addr11
addr16
Call Subroutine only at 2k bytes Address
Call Subroutine in max 64K bytes Address
Return from subroutine
2
3
1
1
2
3
2
1
2
2
2
2
2
2
2
2
2
2
2
2
Return from interrupt
addr11
addr16
rel
@A+DPTR
rel
Jump only at 2k bytes Address
Jump to max 64K bytes Address
Jump on at 256 bytes
Jump to A+ DPTR
Jump if A = 0
JZ
JNZ
rel
Jump if A ≠ 0
CJNE
CJNZ
CJNZ
CJNZ
A, direct,rel
A, #data,rel
Rn, #data,rel
@Ri, #data,rel
3
3
3
3
2
2
2
2
Jump if A ≠ < direct >
Jump if A ≠ < #data >
Jump if Rn ≠ < #data >
Jump if @Ri ≠ < #data >
Decrement and jump if Rn not zero
Decrement and jump if direct not zero
No Operation
DJNZ
DJNZ
NOP
Rn,rel
direct,rel
2
3
1
2
2
1
Limited on Certain Instructions
Branching instructions:
The certain instructions related to branching or jumping should be restricted. When the programmer execute the
branching instructions like AJMP, LJMP, ACALL, LCALL, SJMP etc..., they have responsibility to ensure that the
destination branching address don’t be over internal program memory size. SM894051 contain 4K bytes program
memory and its location is from 00H to 0FFFH.
Data Memory, MOVX-related instructions:
SM894051 contains 128 bytes internal data memory, and it doesn’t support external data memory access. Therefore,
SM894051 doesn’t include MOVX instructions.
Limited on down mode wake-up
SM894051 has two ways to wake-up power down mode. One of them is hardware reset. The other one is that using
external interrupt (#INT0, #INT1) to wake-up power down mode and the external interrupt must be set for level
trigger.
I/O Pin Configuration
Port 1:
The ports P1.2 to P1.7 have internal pull-up resistor. The ports P1.0 to P1.1 are open-drain configuration, so they
require external pull-up resistor to pull low. And P1.0 and P1.1 also used as the positive input (AIN0) and the
negative input (AIN1) of the on chip analog comparator.
As long as the voltage level of P1.0 is greater than P1.1, the output voltage level of the on-chip analog comparator is
“1 “. And this result will be stored in the bit 6 of the port 3 SFR.
Port 3:
The Port 3 are 7-bits bi-directional I/O pins which include P3.0 to P3.5 and P3.7. The P3.6 doesn't be used as general
purpose I/O pin, and the output pin of the on-chip analog comparator connects to the P3.6 which is hard-wired as an
input.
Specifications subject to change without notice contact your sales representatives for the most recent information.
SM894051 V1.4 09 /2006
10
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
