SyncMOS Technologies Inc.
May 2001
Watch Dog Timer Registers - WDT Control Register (WDTC, $9F)
WDTE
Reset
value
0
MSB
WDTE : Watch Dog Timer enable bit
CLEAR : Watch Dog Timer reset bit
PS2 ~ PS0 : clock source divider bit
PS [2:0]
000
001
010
011
100
101
110
111
Divider (OSC in)
8
16
32
64
128
256
512
1024
Time Period (ms) @40MHZ
13.1
26.21
52.42
104.8
209.71
419.43
838.86
1677.72
Unused
*
CLEAR
0
Unused
*
Unused
*
PS2
0
PS1
0
SM8051/8052
PS0
0
LSB
Watch Dog Timer Register - System Control Register (SCONF, $BF)
WDR
Reset
value
0
MSB
Unused
*
Unused
*
Unused
*
Unused
*
Unused
*
Unused
*
ALEI
0
LSB
WDR : Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1
ALEI : ALE output inhibit bit, to reduce EMI
The bit 7(WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated
by WDT overflow. User should check WDR bit whenever un-predicted reset happened.
Reduce EMI Function
The SM8051/8052 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This
function will inhibit the clock signal in Fosc/6Hz output to the ALE pin. This function is available when there is
no external program memory or no external data RAM in the system.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
6/16
Ver 1.1
SM8051/8052 07/2005
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
