SyncMOS Technologies Inc.
May 2001
SM8051/80952
Tm.II External Data Memory Read Cycle
#PSEN
ALE
TYHLH
TLLDV
TLLYL
TRLRH
#RD
TAVLL
TLLAX
TRHDZ
TRHDX
DATA IN
TRLDV
TRLAZ
A0 - A7
A0 - A7
from PCL
INSTRL
IN
PORT 0
PORT 2
from Ri or DPL
TAVYL
TAVDV
A8 - A15 from PCH
P2.0 - P2.7 or A8 - A15 from DPH
Tm.III External Data Memory Write Cycle
#PSEN
TYHLH
TLHLL
ALE
TLLYL
TWLWH
TQVWH
TAVLL
#WR
TQVWX
TLLAX
TWHQX
A0-A7
from Ri or DPL
A0-A7
From PCL
INSTRL
IN
DATA OUT
PORT 0
TAVYL
A8-A15 from PCH
P2.0-P2.7 or A8-A15 from DPH
PORT 2
Specifications subject to change without notice,contact your sales representatives for the most recent information.
12/16
Ver 1.1
SM8051/8052 07/2005
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
