SyncMOS Technologies Inc.
May 2001
Block Diagram
Stack
Pointer
Decoder &
Register
128/256
bytes RAM
SM8051/80952
Timer 2
Timer 1
Timer 0
WDT
RES
Reset
Circuit
to pertinent blocks
Acc
to whole chip
Buffer2
Buffer1
Buffer
DPTR
Vdd
Vss
Power
Circuit
PC
Incrementer
Interrupt
Circuit
to pertinent blocks
ALU
Program
Counter
PSW
XTAL2
XTAL1
#EA
ALE
#PSEN
to whole system
Timing
Generator
Register
Instruction
Register
4/8 K
bytes
Port 0
Latch
Port 1
Latch
Port 2
Latch
Port 3
Latch
ROM
Memory
Port 0
Driver & Mux
8
Port 1
Driver & Mux
8
Port 2
Port 3
Driver & Mux Driver & Mux
8
8
Specifications subject to change without notice,contact your sales representatives for the most recent information.
3/16
Ver 1.1
SM8051/8052 07/2005
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
