SyncMOS Technologies International. Inc.
SM79164
RAMS3
RAMS2
RAMS1
RAMS0
MOVX @Ri i=0,1 mapping to expended RAM address
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
$0000 ~ $00FF
$0100 ~ $01FF
$0200 ~ $02FF
$0300 ~ $03FF
$0400 ~ $04FF
$0500 ~ $05FF
$0600 ~ $06FF
$0700 ~ $07FF
$0800 ~ $08FF
$0900 ~ $09FF
$0A00 ~ $0AFF
$0B00 ~ $0BFF
$0C00 ~ $0CFF
$0D00 ~ $0DFF
$0E00 ~ $0EFF
The port 0, port2, port3.6 and port3.7 can be used as general purpose I/O pin while port0 is open-drain structure.
System Control Register (SCONF, $BF)
bit-7
WDR
R/W
0
bit-0
Unused
Unused
Unused
Unused
Unused
OME
R/W
0
ALEI
R/W
0
Read / Write:
Reset value:
-
-
-
-
-
*
*
*
*
*
WDR : Watch Dog Timer Reset.
OME : 3840 bytes on-chip RAM enable bit
ALEI : ALE output inhibit bit, to reduce EMI
Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz output to the ALE pin.
The bit 1 (OME) of SCONF can enable or disable the on-chip expanded 3840 byte RAM. The default setting of OME bit is
0 (disable).
The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow.
User should check WDR bit whenever un-predicted reset happened.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
10/26
Ver 2.1 SM79164 08/2006
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
