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SM59R05A5C25 参数 Datasheet PDF下载

SM59R05A5C25图片预览
型号: SM59R05A5C25
PDF下载: 下载PDF文件 查看货源
内容描述: SM59R16A5 / SM59R09A5 / SM59R05A5\n8位微控制器\n64KB / 36KB / 20KB具有ISP功能的Flash\n和2KB RAM的嵌入式 [SM59R16A5/SM59R09A5/SM59R05A5 8-Bit Micro-controller 64KB/36KB/20KB with ISP Flash & 2KB RAM embedded]
分类和应用: 微控制器
文件页数/大小: 89 页 / 3025 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
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SM59R16A5/SM59R09A5/SM59R05A5  
8-Bit Micro-controller  
64KB/36KB/20KB with ISP Flash  
& 2KB RAM embedded  
001  
010  
011  
100  
101  
110  
111  
Fosc/64  
Fosc/128  
Fosc/256  
Fosc/512  
Fosc/1024  
Fosc/2048  
Fosc/4096  
Mnemonic: IICS  
Address: F8h  
7
6
5
4
3
2
1
0
Reset  
MStart  
RxIF  
TxIF  
RDR  
TDR  
RxAK  
TxAK  
RW  
00h  
MStart: Master Start control bit. (Master mode only)  
If set the MStart bit, the module will generate a start condition to the SDA and SCL lines  
and send out the calling address which is stored in the IICA1 or IICA2 (selected by MAS  
control bit). When software cleared this bit, the module will generate a stop condition to  
the SDA and SCL.  
RxIF: The data Receive Interrupt Flag (RXIF) is set after the IICRWD (IIC Read Write Data  
Buffer) is loaded with a newly receive data.  
TxIF: The data Transmit Interrupt Flag (TXIF) is set when the data of the IICRWD (IIC Read  
Write Data Buffer) is downloaded to the shift register.  
RDR: The MCU must clear this bit after it gets the data from IICRWD. The IIC module is able to  
write new data into IICRWD only when this bit is cleared.  
TDR: When MCU finish writing data to IICRWD, the MCU needs to set this bit to ‘1’ to inform  
the IIC module to send the data in the IICRWD. After IIC module finishes sending the  
data from IICRWD, this bit will be cleared automatically.  
RxAK: The Acknowledge Status indicate bit. When clear, it means an acknowledge signal has  
been received after the complete 8 bits data transmit on the bus.  
TxAK: The Acknowledge status transmit bit. When received complete 8 bits data, this bit will set  
(NoAck) or clear (Ack) and transmit to master to indicate the receive status. Actually, it is  
sent as the 9th bit in one byte transmission as show in Fig. 14-1.  
RW: The slave mode read (received) or wrote (transmit) on the IIC bus. When this bit is clear,  
the slave module received data on the IIC bus (SDA).(Slave mode only)  
Fig. 14-1: Acknowledgement bit in the 9th bit of a byte transmission  
Mnemonic: IICA1  
Address: FAH  
7
6
5
4
3
2
1
0
Reset  
Match1 or  
RW1  
R or R/W  
IICA1[7:1]  
R/W  
A0H  
Specifications subject to change without notice contact your sales representatives for the most recent information.  
ISSFD-M047 61 Ver.G SM59R16A5 01/2014  
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