SM59R16A5/SM59R09A5/SM59R05A5
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
10. Watchdog timer
The Watch Dog Timer (WDT) is an 8-bit free-running counter that generate reset signal if the counter overflows. The WDT
is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software
dead loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is
different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically
clearing the WDT counter. User should check WDTF bit of WDTC register whenever un-predicted reset happened. After
an external reset the watchdog timer is disabled and all registers are set to zeros.
The watchdog timer has a free running on-chip RC oscillator (250KHz ±20%). The WDT will keep on running even after
the system clock has been turned off (for example, in sleep mode). During normal operation or sleep mode, a WDT
time-out (if enabled) will cause the MCU to reset. The WDT can be enabled or disabled any time during the normal mode.
Please refer the WDTE bit of WDTC register. The default WDT time-out period is approximately 16.38ms (WDTM [3:0] =
0100b).
The WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit3 ~ bit0
(WDTM [3:0]) of Watch Dog Timer Control Register (WDTC) should be set accordingly.
250KHz
WDTCLK =
2WDTM
256
Watchdog reset time =
WDTCLK
Table 10.1 WDT time-out period
Divider
(250 KHz RC oscillator in)
WDTM [3:0]
Time period @ 250KHz
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
2
4
8
16
1.02ms
2.05ms
4.10ms
8.19ms
16.38ms (default)
32.77ms
65.54ms
131.07ms
262.14ms
524.29ms
1.05s
32
64
128
256
512
1024
2048
4096
8192
16384
32768
2.10s
4.19s
8.39s
16.78s
33.55s
When MCU is reset, the MCU will be read WDTEN control bit status. When WDTEN bit is set to 1, the watchdog function
will be disabled no matter what the WDTE bit status is. When WDTEN bit is clear to 0, the watchdog function will be
enabled if WDTE bit is set to 1 by program. User can to set WDTEN on the writer or ISP.
The program can enable the WDT function by programming 1 to the WDTE bit premise that WDTEN control bit is clear to
0. After WDTE set to 1, the 8 bit-counter starts to count with the selected time base source clock which set by WDTM [3:0].
It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when MCU been reset,
either hardware reset or WDT reset.
Once the watchdog is started it cannot be stopped. User can refreshed the watchdog timer to zero by writing 0x55 to
Watch Dog Timer refresh Key (WDTK) register. This will clear the content of the 8-bit counter and let the counter re-start
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M047
48
Ver.G SM59R16A5 01/2014
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
