SM59R16A5/SM59R09A5/SM59R05A5
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Pin Configuration
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
VDD
CC0/T2/ADC0/P1.0
P0.0/AD0/KBI0
CC1/T2EX/ADC1/P1.1
RXD1/ADC2/P1.2
CC2/TXD1/ADC3/P1.3
CC3/SS/ADC4/P1.4
MOSI/ADC5/P1.5
IIC_SCL/MISO/ADC6/P1.6
IIC_SDA/SPI_CLK/ADC7/P1.7
P4.7/RESET(default)
RXD0/P3.0
3
P0.1/AD1/KBI1
4
P0.2/AD2/KBI2
5
P0.3/AD3/KBI3
6
P0.4/AD4/KBI4
7
P0.5/AD5/KBI5
8
P0.6/AD6/KBI6
9
P0.7/AD7/KBI7
10
11
12
13
14
15
16
17
18
19
20
OCI_SDA/P4.6
ALE/P4.5
TXD0/P3.1
OCI_SCL/P4.4
INT0/P3.2
P2.7/A15/KBI7/Op0Out/PWM3
P2.6/A14/KBI6/Op0PIn/PWM2
P2.5/A13/KBI5/Op0NIn/PWM1
P2.4/A12/KBI4/Op1PIn/PWM0
P2.3/A11/KBI3/Op1NIn/CC3
P2.2/A10/KBI2/Op1Out/CC2
P2.1/A9/KBI1/CC1
P2.0/A8/KBI0/CC0
INT1/P3.3
T0/P3.4
T1/P3.5
X32OUT/WR/P3.6
X32IN/RD/P3.7
X32OUT/P5.4/XTAL2
X32IN/P5.5/XTAL1
VSS
Notes：
1. The pin Reset/P4.7 factory default is Reset, user must keep this pin at low during power-up. User can configure it to
GPIO (P4.7) by a flash programmer.
2. To avoid accidentally entering ISP-Mode(refer to section 16.4), care must be taken not asserting pulse signal at P3.0
during power-up while P2.6、P2.7、P4.3 are set to high.
3. To apply ICP function, OSI_SDA/P4.6 and OCI_SCL/P4.7 must be set to Bi-direction mode if they are configured as
GPIO in system.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M047
4
Ver.G SM59R16A5 01/2014
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
