SM59R16A5/SM59R09A5/SM59R05A5
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
100: Capture on rising edge at pin CC0
101: Capture on falling edge at pin CC0
110: Capture on both rising and falling edge at pin CC0
111: Capture on write operation into register CC0
Mnemonic: CCEN2
7
6
5
4
--
COCAM3[2:0]
3
--
Address: D1h
2
1
0
Reset
COCAM2[2:0]
00H
COCAM3[2:0] 000: Compare/Capture disable
001: Compare enable but no output on Pin
010: Compare mode 0
011: Compare mode 1
100: Capture on rising edge at pin CC3
101: Capture on falling edge at pin CC3
110: Capture on both rising and falling edge at pin CC3
111: Capture on write operation into register CC3
COCAM2[2:0] 000: Compare/Capture disable
001: Compare enable but no output on Pin
010: Compare mode 0
011: Compare mode 1
100: Capture on rising edge at pin CC2
101: Capture on falling edge at pin CC2
110: Capture on both rising and falling edge at pin CC2
111: Capture on write operation into register CC2
8.1.
Timer 2 function
Timer 2 can operate as timer, event counter, or gated timer as explained later.
8.1.1.
Timer mode
In this mode Timer 2 can by incremented in various frequency that depending on the prescaler. The prescaler is selected
by bit T2PS[2:0] in register T2CON.
8.1.2.
Event counter mode
In this mode, the timer is incremented when external signal T2 change value from 1 to 0. The T2 input is sampled in
every cycle. Timer 2 is incremented in the cycle following the one in which the transition was detected.
8.1.3.
Gated timer mode
In this mode, the internal clock which incremented timer 2 is gated by external signal T2.
8.1.4.
Reload of Timer 2
Reload (16-bit reload from the crc register) can be executed in the following two modes:
Mode 0: Reload signal is generate by a Timer 2 overflows - auto reload
Mode 1: Reload signal is generate by a negative transition at the corresponding input pin T2EX.
8.2.
Compare function
In the four independent comparators, the value stored in any compare/capture register is compared with the contents of
the timer register. The compare modes 0 and 1 are selected by bits C0CAMx. In both compare modes, the results of
comparison arrives at Port 1 within the same machine cycle in which the internal compare signal is activated.
When the channel 1、2 and 3 use at compare function，The compare mode setting of Channel 2 and Channel 3 should be
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M047
39
Ver.G SM59R16A5 01/2014
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
