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SM59R05A5C25 参数 Datasheet PDF下载

SM59R05A5C25图片预览
型号: SM59R05A5C25
PDF下载: 下载PDF文件 查看货源
内容描述: SM59R16A5 / SM59R09A5 / SM59R05A5\n8位微控制器\n64KB / 36KB / 20KB具有ISP功能的Flash\n和2KB RAM的嵌入式 [SM59R16A5/SM59R09A5/SM59R05A5 8-Bit Micro-controller 64KB/36KB/20KB with ISP Flash & 2KB RAM embedded]
分类和应用: 微控制器
文件页数/大小: 89 页 / 3025 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
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SM59R16A5/SM59R09A5/SM59R05A5  
8-Bit Micro-controller  
64KB/36KB/20KB with ISP Flash  
& 2KB RAM embedded  
Function Description  
1. General Features  
SM59R16A5 is an 8-bit micro-controllerAll of its functions and the detailed meanings of SFR will be given in the following  
sections。  
1.1. Embedded Flash  
The program can be loaded into the embedded 64KB/36KB/20KB Flash memory via writer or In-System Programming  
(ISP)。  
1.2. IO Pads  
The SM59R16A5 has six I/O ports: Port 0, Port 1, Port 2, Port 3, Port 4, and Port 5. Ports 0, 1, 2, 3, 4 are 8-bit ports and  
Port 5 is a 6-bit port. These are: quasi-bidirectional (standard 8051 port outputs), push-pull, open drain, and input-only. As  
description in section 5。  
The OCI_SCLALEOCI_SDA and RESET can be configured as I/O ports P4.4P4.5P4.6 and P4.7 by writer or in ISP  
mode.  
The XTAL2 and XTAL1 can be configured as I/O ports P5.4 and P5.5 by writer or in ISP mode, when the on-chip  
RC-Oscillator is set to main system clock source.  
All the pins on P0 ~ P5 are with slew rate adjustment to reduce EMI. The other way to reduce EMI is to disable the ALE  
output if unused. This is selected by its SFR. The IO pads can withstand 4KV ESD in human body mode guaranteeing the  
SM59R16A5’s quality in high electro-static environments.  
1.3. 2T/1T Selection  
The conventional 52-series MCUs are 12T, i.e., 12 oscillator clocks per machine cycle. SM59R16A5 is a 2T or 1T MCU,  
i.e., its machine cycle is two-clock or one-clock. In the other words, it can execute one instruction within two clocks or  
only one clock. The difference between 2T mode and 1T mode are given in the example in Fig. 1-1.  
Fig. 1-1(a): The waveform of internal instruction signal in 2T mode  
Fig. 1-1(b): The waveform of internal instruction signal in 1T mode  
The default is in 2T mode, and it can be changed to 1T mode if IFCON [7] (at address 8Fh) is set to high any time. Not  
every instruction can be executed with one machine cycle. The exact machine cycle number for all the instructions are  
given in the next section.  
Specifications subject to change without notice contact your sales representatives for the most recent information.  
ISSFD-M047  
15  
Ver.G SM59R16A5 01/2014  
 
 
 
 
 
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