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SM59R16A5C25 参数 Datasheet PDF下载

SM59R16A5C25图片预览
型号: SM59R16A5C25
PDF下载: 下载PDF文件 查看货源
内容描述: SM59R16A5 / SM59R09A5 / SM59R05A5\n8位微控制器\n64KB / 36KB / 20KB具有ISP功能的Flash\n和2KB RAM的嵌入式 [SM59R16A5/SM59R09A5/SM59R05A5 8-Bit Micro-controller 64KB/36KB/20KB with ISP Flash & 2KB RAM embedded]
分类和应用: 微控制器
文件页数/大小: 89 页 / 3025 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
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SM59R16A5/SM59R09A5/SM59R05A5  
8-Bit Micro-controller  
64KB/36KB/20KB with ISP Flash  
& 2KB RAM embedded  
SM20: Enables multiprocessor communication feature  
REN0: If set, enables serial reception. Cleared by software to disable reception.  
TB80: The 9th transmitted data bit in modes 2 and 3. Set or cleared by the CPU  
depending on the function it performs such as parity check, multiprocessor  
communication etc.  
RB80: In modes 2 and 3, it is the 9th data bit received. In mode 1, if SM20 is 0, RB80  
is the stop bit. In mode 0, this bit is not used. Must be cleared by software.  
TI0: Transmit interrupt flag, set by hardware after completion of a serial transfer.  
Must be cleared by software.  
RI0: Receive interrupt flag, set by hardware after completion of a serial reception.  
Must be cleared by software.  
Mnemonic: S1CON  
Address: 9Bh  
7
6
5
4
3
2
1
0
Reset  
SM  
-
SM21  
REN1  
TB81  
RB81  
TI1  
RI1  
00h  
SM: Serial Port 1 mode select.  
SM  
0
1
Mode  
A
B
The 2 modes in UART1, Mode A and Mode B, are explained later.  
SM21: Enables multiprocessor communication feature.  
REN1: If set, enables serial reception. Cleared by software to disable reception.  
TB81: The 9th transmitted data bit in mode A. Set or cleared by the CPU depending on  
the function it performs such as parity check, multiprocessor communication  
etc.  
RB81: In mode A, it is the 9th data bit received. In mode B, if SM21 is 0, RB81 is the  
stop bit. Must be cleared by software.  
TI1: Transmit interrupt flag, set by hardware after completion of a serial transfer.  
Must be cleared by software.  
RI1: Receive interrupt flag, set by hardware after completion of a serial reception.  
Must be cleared by software.  
9.1. Serial interface 0  
The Serial Interface 0 can operate in the following 4 modes:  
SM0  
SM1  
Mode  
Description  
Shift register  
8-bit UART  
9-bit UART  
9-bit UART  
Board Rate  
0
0
1
1
0
1
0
1
0
1
2
3
Fosc/12  
Variable  
Fosc/32 or Fosc/64  
Variable  
Here Fosc is the crystal or oscillator frequency.  
9.1.1. Mode 0  
Pin RXD0 serves as input and output. TXD0 outputs the shift clock. 8 bits are transmitted with LSB first. The baud  
rate is fixed at 1/12 of the crystal frequency. Reception is initialized in Mode 0 by setting the flags in S0CON as follows:  
RI0 = 0 and REN0 = 1. In the other modes, a start bit when REN0 = 1 starts receiving serial data.  
Specifications subject to change without notice contact your sales representatives for the most recent information.  
ISSFD-M047  
43  
Ver.G SM59R16A5 01/2014