SyncMOS Technologies International, Inc.
1.3 System Control Register (SCONF, $BF)
bit-7
WDR
Read / Write:
Reset value:
R/W
0
Unused
-
*
Unused
-
*
Unused
-
*
DFEN
-
*
ISPE
R/W
0
OME
R/W
1
SM5964
8-Bits Micro-controller
64KB ISP flash & 1KB RAM embedded
bit-0
ALEI
R/W
0
WDR: Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1.
ISPE: ISP function enable bit
OME: 768 bytes on-chip RAM enable bit .
ALEI: ALE output inhibit bit, to reduce EMI .
Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz output to the ALE pin.
The bit 1 (OME) of SCONF can enable or disable the on-chip expanded 768 byte RAM. The default setting of OME bit is 1
(enable).
The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User
should check WDR bit whenever un-predicted reset happened.
2. Port 4 for PLCC or QFP package:
The bit addressable port 4 is available with PLCC or QFP package. The port 4 has only 4 pins and its port address is
located at 0D8H. The function of port 4 is the same as the function of port 1, port 2 and port 3.
Port4 (P4, $D8)
bit-7
Unused
Read / Write:
-
Unused
-
Unused
-
Unused
-
P4.3
R/W
P4.2
R/W
P4.1
R/W
1
bit-0
P4.0
R/W
1
Reset value:
*
*
*
*
1
1
The bit 3, bit 2, bit 1, bit 0 output the setting to pin P4.3, P4.2, P4.1, P4.0 respectively.
Specifications subject to change without notice contact your sales representatives for the most recent information.
Ver 2.2 SM5964 08/2006
8
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
