SM5964B
8-Bit Micro-controller
64KB with ISP Flash
& 1KB RAM embedded
2. Instruction Set
All SM5964B instructions are binary code compatible and perform the same functions as they do with the industry
standard 8051. The following tables give a summary of the instruction set cycles of the SM5964B Microcontroller
core.
Table 2-1: Arithmetic operations
Mnemonic
ADD A,Rn
Description
Add register to accumulator
Code
28-2F
25
Bytes Cycles
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
4
4
1
ADD A,direct
ADD A,@Ri
ADD A,#data
ADDC A,Rn
ADDC A,direct
ADDC A,@Ri
ADDC A,#data
SUBB A,Rn
SUBB A,direct
SUBB A,@Ri
SUBB A,#data
INC A
Add direct byte to accumulator
Add indirect RAM to accumulator
Add immediate data to accumulator
Add register to accumulator with carry flag
Add direct byte to A with carry flag
Add indirect RAM to A with carry flag
Add immediate data to A with carry flag
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate data from A with borrow
Increment accumulator
26-27
24
38-3F
35
36-37
34
98-9F
95
96-97
94
04
INC Rn
Increment register
08-0F
05
INC direct
INC @Ri
Increment direct byte
Increment indirect RAM
06-07
A3
INC DPTR
DEC A
Increment data pointer
Decrement accumulator
14
DEC Rn
Decrement register
18-1F
15
DEC direct
DEC @Ri
MUL AB
Decrement direct byte
Decrement indirect RAM
16-17
A4
Multiply A and B
DIV
Divide A by B
84
DA A
Decimal adjust accumulator
D4
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M081 Ver A SM5964B 3/7/2014
- 13 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
