SM5958
8-Bit Micro-controller
32KB with ISP Flash
& 1KB RAM embedded
Mnemonic
Description
Dir.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
Watchdog Timer
Watchdog
WDTC
Timer Control
Register
System Control
Register
9FH WDTE
-
-
CLEAR
-
-
-
PS [2:0]
OME
00H
02H
SCONF
BFH
WDR
-
PDWUE
ISPE
ALEI
Mnemonic: WDTC
Address: 9Fh
7
6
-
5
4
-
3
-
2
1
0
Reset
00H
WDTE
CLEAR
PS [2:0]
WDTE: Watch Dog Timer enable bit.
CLEAR: Watch Dog Timer clear bit.
If CLEAR bit set to1, setting this bit the Watchdog timer counter clear and re-start to
count from the Beginning.
PS[2:0]: Watch Dog timer over flow period setting.
Mnemonic: SCONF
Address: BFh
7
6
-
5
-
4
3
-
2
1
0
ALEI
Reset
02H
WDR
PDWUE
ISPE
OME
WDR Watch Dog Timer Reset.
When system reset by Watch Dog Timer overflow, WDR will be set to 1.
User should check WDR bit whenever un-predicted reset happened.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M089 Ver A SM5958 3/19/2014
- 41 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
