SyncMOS Technologies International, Inc.
SM59364
8-Bits Micro-controller
64KB ISP flash & 1KB RAM embedded
page erase function will erase from $XY00 to $X(Y+1)FF (Y:even number), or
page erase function will erase from $X(Y-1) 00 to $XYFF (Y:odd number)
To perform the chip erase ISP function, SM59364 will erase all the flash program memory except the ISP service
program space, also, SM59364 will un-protect the flash memory automatically. To perform chip protect ISP function,
the SM59364 flash memory content will be read #00H.
e.g. ISP service program to do the byte program - to program #22H to the address $1005H
MOV SCONF,#04H
MOV ISPFAH,#10H
MOV ISPFAL,#05H
MOV ISPFD,#22H
MOV ISPC,#80H
; enable SM59364 ISP function
; set flash address-high, 10H
; set flash address-low, 05H
; set flash data to be programmed, data = 22H
; start to program #22H to the flash address $1005H
; after byte program finished, START bit of ISPC will be reset to 0 automatically
; program counter then point to the next instruction
ISP Registers - System Control Register (SCONF,$BF)
bit-7
bit-0
WDR
R/W
0
Unused
Unused
Unused
Unused
ISPE
R/W
0
OME
R/W
1
ALEI
Read / Write:
Reset value:
-
-
-
-
R/W
0
*
*
*
*
The bit 2 (ISPE) of SCONF is ISP enable bit. User can enable overall SM59364 ISP function by setting ISPE bit to 1, to
disable overall ISP function by set ISPE to 0.
The function of ISPE behaves like a security key. User can disable overall ISP function to prevent software program be
erased accidentally.
3. Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The
WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing
software dead loop or runaway. The WDT function can help user software recover form abnormal software condition.
The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by
software periodically clearing the WDT counter. User should check WDR bit of SCONF register whenever un-predicted
reset happened
The WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit2~bit0
(PS2~PS0) of Watch Dog Timer Control Register (WDTC) should be set accordingly.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to
count with the selected time base source clock which set by PS2~PS0. It will generate a reset signal when overflows.
The WDTE bit will be cleared to 0 automatically when SM59364 been reset, either hardware reset or WDT reset.
To reset the WDT is done by setting 1 to the CLEAR bit of WDTC. This will clear the content of the 16-bit counter and
let the counter re-start to count from the beginning.
Specifications subject to change without notice contact your sales representatives for the most recent information.
IDMMX-0033
Ver B SM59364 04/2008
10
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
