SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Once the watchdog is started it cannot be stopped. User can refreshed the watchdog timer to zero by writing 0x55 to
Watch Dog Timer refresh Key (WDTK) register. This will clear the content of the 8-bit counter and let the counter re-start
to count from the beginning. The watchdog timer must be refreshed regularly to prevent reset request signal from
becoming active.
When Watchdog timer is overflow, the WDTF flag will set to one and automatically reset MCU. The WDTF flag can be
clear by software or external reset or power on reset.
Clear
WDTF = 0
Power on reset
External reset
Software write “0”
23KHz RC
oscillator
WDTF
Set WDTF = 1
WDT time-out reset
WDTCLK
1
TAKEY
(55, AA, 5A)
WDT
Counter
2WDTM
WDTM[3:0]
Enable/Disable
WDT
Refresh
WDT Counter
WDTC
Enable WDTC
write attribute
WDTK
(0x55)
WDTEN
Fig. 8-1: Watchdog timer block diagram
Mnemonic
Description
Direct Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 RESET
Watchdog Timer
Time Access
Key register
Watchdog
timer control
register
TAKEY
WDTC
F7h
B6h
TAKEY [7:0]
-
00H
04H
CWDTR WDTE
WDTM [3:0]
Watchdog
timer refresh
key
Reset status
register
WDTK
RSTS
B7h
WDTK[7:0]
00H
00H
A1h
-
-
-
PDRF WDTF SWRF LVRF PORF
Mnemonic: TAKEY
Address: F7h
7
6
5
4
3
2
1
0
Reset
00H
TAKEY [7:0]
Watchdog timer control register (WDTC) is read-only by default; software must write three specific
values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the WDTC write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver B SM39R08A5 04/22/2013
- 30 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
