SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
7. Serial interface
The serial buffer consists of two separate registers, a transmit buffer and a receive buffer.
Writing data to the Special Function Register SBUF sets this data in serial output buffer and starts the transmission.
Reading from the SBUF reads data from the serial receive buffer. The serial port can simultaneously transmit and receive
data. It can also buffer 1 byte at receive, which prevents the receive data from being lost if the CPU reads the first byte
before transmission of the second byte is completed.
Mnemonic
Description
Direct Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Bit 1
Bit 0 RESET
Serial interface 0
PCON
AUX
Power control
Auxiliary register
Serial Port
control register
Serial Port
87H
91h
SMOD
BRGS
-
-
-
-
-
-
-
STOP IDLE
40H
00H
PTS[1:0]
PINTS[1:0]
DPS
RI
SCON
SBUF
98H
99H
SM0
SM1
SM2
REN TB8
RB8 TI
00H
00H
SBUF[7:0]
data buffer
Serial Port
reload register
low byte
Serial Port
reload register
high byte
SREL SREL SREL SREL SREL SREL SREL SREL
SRELL
SRELH
AAH
BAH
00H
00H
.7
.6
.5
.4
.3
1
.2
.1
.0
SREL SREL
.9 .8
-
Mnemonic: AUX
Address: 91h
0
7
6
-
5
-
4
3
2
Reset
00H
BRGS
PTS[1:0]
PINTS[1:0]
DPS
BRGS: BRGS = 0 –Baud rate generator use Timer 1 TH1 SFR.
BRGS = 1 –Baud rate generator use SREL SFR.
Mnemonic: SCON
Address: 98h
7
SM0
6
SM1
5
SM2
4
REN
3
TB8
2
RB8
1
TI
0
RI
Reset
00h
SM0,SM1: Serial Port mode selection.
SM0 SM1
Mode
0
0
1
1
0
1
0
1
0
1
2
3
The 4 modes in UART, Mode 0 ~ 3, are explained later.
SM2: Enables multiprocessor communication feature
REN: If set, enables serial reception. Cleared by software to disable reception.
TB8: The 9th transmitted data bit in modes 2 and 3. Set or cleared by the CPU
depending on the function it performs such as parity check, multiprocessor
communication etc.
RB8: In modes 2 and 3, it is the 9th data bit received. In mode 1, if SM2 is 0, RB8 is
the stop bit. In mode 0, this bit is not used. Must be cleared by software.
TI: Transmit interrupt flag, set by hardware after completion of a serial transfer.
Must be cleared by software.
RI: Receive interrupt flag, set by hardware after completion of a serial reception.
Must be cleared by software.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver B SM39R08A5 04/22/2013
- 25 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
