SM39A16M1
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Mnemonic:IRCON2
Address: 97h
7
-
6
-
5
-
4
-
3
-
2
1
0
-
Reset
00H
CmpIF
WDTIF
CmpIF Comparator interrupt flag
HW will clear this flag automatically when enter interrupt vector.
SW can clear this flag also.(in case analog comparator INT disable)
WDTIF: Watch dog interrupt flag
11.1 Priority level structure
All interrupt sources are combined in groups, As given in Table 11-2.
Table 11-2: Priority level groups
Groups
External interrupt 0
Timer 0 interrupt
-
PWM interrupt
Watchdog interrupt
SPI interrupt
ADC interrupt
External interrupt 1
Timer 1 interrupt
Comparator interrupt
-
-
-
Serial channel 0 interrupt
Timer 2 interrupt
LVI interrupt
IIC interrupt
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one
bit in the special function register ip0 and one in ip1. If requests of the same priority level will be received
simultaneously, an internal polling sequence determines which request is serviced first. As given in Table 11-3 and
Table 11-4 and Table 11-5.
Mnemonic: IP0
Address: A9h
7
-
6
-
5
4
3
2
1
0
Reset
00h
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
Mnemonic: IP1
Address: B9h
7
-
6
-
5
4
3
2
1
0
Reset
00h
IP1.5
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
Table 11-3: Priority levels
IP1.x
IP0.x
Priority Level
Level0 (lowest)
0
0
1
1
0
1
0
1
Level1
Level2
Level3 (highest)
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M069 Ver C SM39A16M1 7/31/2013
- 61 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
