SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
8.11.3 Gated Timer Mode
In this mode, the internal clock which incremented timer 2 is gated by external signal T2. As shown in Fig. 8-4
Fig. 8-4: Gated timer mode function
8.11.4 Reload of Timer 2
Reload (16-bit reload from the crc register) can be executed in the following two modes:
Mode 0: Reload signal is generate by a Timer 2 overflows - auto reload
Mode 1: Reload signal is generate by a negative transition at the corresponding input pin T2EX.
8.12
Compare Function
In the four independent comparators, the value stored in any compare/capture register is compared with the contents
of the timer register. The compare modes 0 and 1 are selected by bits C0CAMx . In both compare modes, the results
of comparison arrives at Port 1 within the same machine cycle in which the internal compare signal is activated.
8.12.1 Compare Mode 0
In mode 0, when the value in Timer 2 equals the value of the compare register, the output signal changes from low to
high. It goes back to a low level on timer overflow. In this mode, writing to the port will have no effect, because the
input line from the internal bus and the write-to-latch line are disconnected. As shown in Fig. 8-5 illustrates the function
of compare mode 0.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071
Ver A SM59A16U1 04/12/2013
- 59 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
