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59A16U1 参数 Datasheet PDF下载

59A16U1图片预览
型号: 59A16U1
PDF下载: 下载PDF文件 查看货源
内容描述: 带USB功能,内嵌64KB具有ISP功能的闪存和6K + 256B RAM的1T 8051控制器59A16U1 [带USB功能,内嵌 64KB具有 ISP 功能的 Flash和 6K+256B RAM的 1T 8051控制器59A16U1]
分类和应用: 闪存控制器
文件页数/大小: 146 页 / 4146 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
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SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
6. Multiplication Division Unit( MDU )
This on-chip arithmetic unit provides 32-bit division, 16-bit multiplication, shift and normalize features, etc. All
operations are unsigned integer operations.
Table 6-1:
乘除寄存器
Dir.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
The relevant registers of the Multiplication Division Unit
87H
SMOD MDUF
-
Multiplication Division Unit
EFh
E9h
MDEF
MDOV
SLR
MD0[7:0]
00H
EAh
MD1[7:0]
00H
EBh
MD2[7:0]
00H
ECh
MD3[7:0]
SC[4:0]
Mnemonic
PCON
ARCON
MD0
Description
Power control
Arithmetic
Control register
Multiplication/Di
vision Register
0
Multiplication/Di
vision Register
1
Multiplication/Di
vision Register
2
Multiplication/Di
vision Register
3
Multiplication/Di
vision Register
4
Multiplication/Di
vision Register
5
Bit 1
STOP
Bit 0
IDLE
RST
40H
00H
00H
MD1
MD2
MD3
MD4
EDh
MD4[7:0]
00H
MD5
EEh
MD5[7:0]
00H
6.1
Operating Registers of the MDU
The MDU is handled by seven registers, which are memory mapped as special function registers. The arithmetic unit
allows operations concurrently to and independent of the CPU‟s activity. Operands and results registers are MD0 to
MD5. Control register is ARCON. Any calculation of the MDU overwrites its operands.
Mnemonic: ARCON
7
6
5
MDEF MDOV
SLR
Address: EFh
0
Reset
00H
4
3
2
SC[4:0]
1
MDEF: Multiplication Division Error Flag.
The MDEF is an error flag. The error flag is read only. The error flag indicates an
improperly performed operation (when one of the arithmetic operations has been
restarted or interrupted by a new operation). The error flag mechanism is automatically
enabled with the first write to MD0 and disabled with the final read instruction from MD3
multiplication or shift/normalizing) or MD5 (division) in phase three.
The error flag is set when:
1. Phase two in process and write access to mdx registers (restart or interrupt
calculations)
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071
Ver A
SM59A16U1
04/12/2013
- 42 -