SPP2305D
P-Channel Enhancement Mode MOSFET
DESCRIPTION
The SPP2305D is the P-Channel logic enhancement
mode power field effect transistors are produced using
high cell density , DMOS trench technology.
This high density process is especially tailored to
minimize on-state resistance.
These devices are particularly suited for low voltage
application such as cellular phone and notebook
computer power management and other battery powered
circuits, and low in-line power loss are needed in a very
small outline surface mount package.
APPLICATIONS
Power Management in Note book
Portable Equipment
Battery Powered System
DC/DC Converter
Load Switch
DSC
LCD Display inverter
FEATURES
-15V/-3.5A,R
DS(ON)
= 70mΩ@V
GS
=-4.5V
-15V/-3.0A,R
DS(ON)
= 85mΩ@V
GS
=-2.5V
-15V/-2.0A,R
DS(ON)
=105mΩ@V
GS
=-1.8V
Super high density cell design for extremely low
R
DS (ON)
Exceptional on-resistance and maximum DC
current capability
SOT-23 package design
PIN CONFIGURATION(SOT-23)
PART MARKING
S05YW
2011/01/03
Ver.1
Page 1