HV738
Pin Description
Pin #
ꢃ, ꢃ2
2, ꢃꢃ
48
Na0e
Function
VDD
VSS
Positiꢀe internal ꢀoltage supply (+8.0V).
Power supply return (0V).
VLL
Logic Hi ꢀoltage reference input (+2.6V).
Logic Low reference, logic ground (0V).
Bleed resistors common return ground. (Both pins must be used)
4ꢁ
GREF
RGND
2±, 36
ꢃ8, ꢃ9, 20,
4ꢃ, 42, 43
2ꢃ, 22, 23,
38, 39, 40
VPP
VNN
Positiꢀe high ꢀoltage power supply (+±6V).
Negatiꢀe high ꢀoltage power supply (-±6V).
ꢃꢁ, 44
24, 3ꢁ
34
33
32
3ꢃ
30
29
28
2ꢁ
3
VPF
P-FET driꢀe floating power supply, (VPP- VPF) = +8.0V.
VNF
N-FET driꢀe floating power supply, (VNF- VNN) = +8.0V.
TXPꢃ
TXNꢃ
TXP2
TXN2
TXP3
TXN3
TXP4
TXN4
PINꢃ
NINꢃ
PIN2
NIN2
PIN3
NIN3
PIN4
NIN4
EN
Output P-FET drain (open drain output) for channel ꢃ.
Output N-FET drain (open drain output) for channel ꢃ.
Output P-FET drain (open drain output) for channel 2.
Output N-FET drain (open drain output) for channel 2.
Output P-FET drain (open drain output) for channel 3.
Output N-FET drain (open drain output) for channel 3.
Output P-FET drain (open drain output) for channel 4.
Output N-FET drain (open drain output) for channel 4.
Input logic control of high ꢀoltage output P-FET of channel ꢃ, Hi=on, Low=off.
Input logic control of high ꢀoltage output N-FET of channel ꢃ, Hi=on, Low=off.
Input logic control of high ꢀoltage output P-FET of channel 2, Hi=on, Low=off.
Input logic control of high ꢀoltage output N-FET of channel 2, Hi=on, Low=off.
Input logic control of high ꢀoltage output P-FET of channel 3, Hi=on, Low=off.
Input logic control of high ꢀoltage output N-FET of channel 3, Hi=on, Low=off.
Input logic control of high ꢀoltage output P-FET of channel 4, Hi=on, Low=off.
Input logic control of high ꢀoltage output N-FET of channel 4, Hi=on, Low=off.
Chip power enable Hi=on, Low=off.
4
6
±
ꢁ
8
9
ꢃ0
4±
ꢃ6
ꢃ4
MC0
MCꢃ
Output current mode control pins, see Driꢀe Mode Control Table.
Oꢀer temperature protection output, open N-FET drain,
actiꢀe low if IC temperature >ꢃꢃ0°C.
ꢃ3
OTP
Substrate of the IC, Substrate bottom is internally connected to the central thermal pad
on the bottom of package.
It must be connected to VSUB, the most positiꢀe potential of the IC externally.
ꢃ±, 26, 3±,
46
Thermal Pad
(VSUB
)
±
SUPERTEX [ Supertex, Inc ]
