HV583
Pad Description
Vpp
Vdd
D1A to D4A
D1B to D4B
Dir
Clk
RST
LE
OE
OL
OH
DGND
PGND
HVout0 to HVout127
High voltage supply for outputs.
Low voltage logic supply
Right data input/output. Input when Dir=H, Output when Dir=L.
Left data input/output. Input when Dir=L, Output when Dir=H.
Dir=L or open, D
XB
to D
XA
shift. Dir=H, D
XA
to D
XB
shift.
Clock input. Data shifted from low to high transition.
Resets latches.
Latch enable. Data latches during rising edge LE.
Output enable bar. HVout high impedance control.
Output low bar. HVout=low when this pin is low.
OH bar input.
Digital logic ground.
HVout output ground.
High voltage outputs.
Pad Location
PGND
PGND
PGND
PGND
V
PP
V
PP
V
PP
V
PP
V
PP
V
PP
HVOUT
64
HVOUT
63
HVOUT
127
V
PP
PGND
HVOUT
0
V
PP
PGND
D
1A
D
2A
D
3A
D
4A
OH
OE
OL
DGND
RST
V
DD
V
DD
DIR
D
4B
D
3B
D
2B
CLK
D
1B
LE
5
DGND
SUPERTEX [ Supertex, Inc ]
