HV5812
Timing Diagram
tpwclk
50%
CLK
50%
tsu
Data In
tpwd
th
tpws
tcks
Strobe
Blanking
50%
tPHL
tPLH
tsto
90% 90%
50%
10%
HVOUT
10%
tr
tf
Block Diagram
Blanking
Strobe
VPP
VDD
HVOUT
1
HVOUT2
HVOUT3
Data In
Clock
Data Out
20-bit
Shift
20-bit
Latch
Register
HVOUT20
GND
Function Table
Serial
Clock Shift Register Contents
Serial
Data
Strobe
Input
Latch Content
Blanking
Output Content
Data
Input
Input
I1 I2
I3 ... IN-1 IN
Output
I1 I2 I3 ... IN-1 IN
I1 I2 I3 ... IN-1 IN
H
L
L to H
L to H
H
L
R1 R2 ... RN-2 RN-1
R1 R2 ... RN-2 RN-1
RN-1
RN-1
RN
X
X
H to L R1 R2 R3 ... RN-1 RN
X ... X
P1 P2 P3 ... PN-1 PN
X
X
X
L
R1 R2 R3 ... RN-1 RN
P1 P2 P3 ... PN-1 PN
PN
H
L
P1 P2 P3 ... PN-1 PN
X
X
X ... X
X
H
L
L
L ... L
L
Note:
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P= Present State
R = Previous State
4
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