HV57708
Functional Block Diagram
D
O
1 D
O
2
D
I
4 D
I
3
D
O
3
D
I
2
D
O
4
D
I
1
V
DD
LE
BL
POL
V
PP
DIR
SR1
HV
OUT
1
5
9
•
•
•
HV
OUT
61
SR2
HV
OUT
2
6
10
•
•
•
HV
OUT
62
CLK
HV
OUT
3
7
11
•
•
•
HV
OUT
63
SR3
SR4
HV
OUT
4
8
12
•
•
•
HV
OUT
64
D
O
4 D
O
3
D
I
1 D
I
2
D
O
2
D
I
3
D
O
1
D
I
4
GND
Note: Each SR (shift register) provides 16 outputs. SR1 supplies every fourth output starting with 1; SR2 supplies every fourth output with 2, etc.
Function Table
Inputs
Function
All O/P High
All O/P Low
O/P Normal
O/P Inverted
Data Falls
Through
(Latches
Transparent)
Data Stored/
Latches Loaded
Data
X
X
X
X
L
H
L
H
X
X
D
I/O
1-4A
D
I/O
1-4A
I/O Relation
D
I/O
1-4B
D
I/O
1-4B
Note:
Outputs
BL
L
L
H
H
H
H
H
H
H
H
H
H
H
H
POL
L
H
H
L
H
H
L
L
H
L
H
H
H
H
DIR
X
X
X
X
X
X
X
X
X
X
H
H
L
L
L
H
L
H
*
*
Q
n
→
Q
n +1
Q
n
→
Q
n +1
Q
n
→
Q
n -1
Q
n
→
Q
n -1
Shift Reg
HV Outputs
H
L
No inversion
Inversion
L
H
H
L
Stored Data
Inversion of
Stored Data
New H or L
Previous
H or L
Previous
H or L
New H or L
D
I/O
1 – 4B
D
I/O
1 – 4B
D
I/O
1 – 4A
D
I/O
1 – 4A
Data Out
CLK
X
X
X
X
↑
↑
↑
↑
X
X
↑
↑
↑
↑
LE
X
X
X
X
H
H
H
H
L
L
H
L
L
H
*
= dependent on previous stage’s state. See Pin configuration for D
IN
and D
OUT
pin designation for CW and CCW shift.
4
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