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HV57708PG 参数 Datasheet PDF下载

HV57708PG图片预览
型号: HV57708PG
PDF下载: 下载PDF文件 查看货源
内容描述: 32兆赫, 64通道串行到并行转换器采用推挽式输出 [32 MHz, 64-Channel Serial To Parallel Converter With Push-Pull Outputs]
分类和应用: 转换器
文件页数/大小: 5 页 / 467 K
品牌: SUPERTEX [ Supertex, Inc ]
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HV57708
Electrical Characteristics
(over recommended operating conditions unless noted, T =-40°C to +85°C)
A
DC Characteristics
Symbol
I
DD
I
PP
I
DDQ
V
OH
V
OL
I
IH
I
IL
V
OC
Parameter
V
DD
supply current
High voltage supply current
Min
Max
15
100
100
Quiescent V
DD
supply current
High-level output
HV
OUT
Data out
Low-level output
HV
OUT
Data out
High-level logic input current
Low-level logic input current
High voltage clamp diode
65
V
DD
- 0.5
7
0.5
1
-1
1
100
Units
mA
µA
µA
µA
V
V
V
V
µA
µA
V
Conditions
V
DD
= V
DD
max
f
CLK
= 8MHz
Outputs high
Outputs low
All V
IN
= V
DD
I
O
= -15mA, V
PP
= 80V
I
O
= -100µA
I
O
= 12mA, V
PP
= 80V
I
O
= 100µA
V
IH
= V
DD
V
IL
= 0V
I
OC
= 1mA
AC Characteristics
(T
A
= 85°C max. Logic signal inputs and Data inputs have t
r
, t
f
5ns [10% and 90% points])
Symbol
f
CLK
t
WL
,t
WH
t
SU
t
H
t
ON
, t
OFF
t
DHL
t
DLH
t
DLE
*
t
WLE
t
SLE
Parameter
Clock frequency
Clock width high or low
Data set-up time before clock rises
Data hold time after clock rises
Time from latch enable to HV
OUT
Delay time clock to data high to low
Delay time clock to data low to high
Delay time clock to LE low to high
Width of LE pulse
LE set-up time before clock rises
25
25
0
62
10
15
500
70
70
Min
Max
8
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
L
= 15pF
C
L
= 15pF
C
L
= 15pF
Conditions
Per Register
*
t
DLE
is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR output to stabilize).
Recommended Operating Conditions
Symbol
V
DD
V
PP
V
IH
V
IL
f
CLK
T
A
Logic supply voltage
Output voltage
High-level input voltage
Low-level input voltage
Clock frequency per register
Operating free-air temperature
Plastic
Ceramic
Note:
Power-up sequence should be the following:
1. Connect ground.
2. Apply V
DD
.
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
4. Apply V
PP
.
5. The V
PP
should not drop below V
DD
or float during operation.
Power-down sequence should be the reverse of the above.
Parameter
Min
4.5
8
V
DD
-0.5V
0
Max
5.5
80
Units
V
V
V
0.5
8
V
MHz
°C
-40
-55
+85
+125
2