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HV57009_07 参数 Datasheet PDF下载

HV57009_07图片预览
型号: HV57009_07
PDF下载: 下载PDF文件 查看货源
内容描述: 64通道串行到并行转换器采用P沟道开漏输出可控制输出电流 [64-Channel Serial to Parallel Converter with P-Channel Open Drain Controllable Output Current]
分类和应用: 转换器
文件页数/大小: 8 页 / 802 K
品牌: SUPERTEX [ Supertex, Inc ]
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HV57009  
Ordering Information  
Package Options  
80-Lead PQFP  
HV57009PG-G  
Device  
HV57009  
-G indicates package is RoHS compliant (‘Green’)  
Absolute Maximum Ratings  
Pin Configuration  
Parameter  
Value  
-0.5V to +7.5V  
VDD + 0.5V to -95V  
-0.3V to VDD + 0.3V  
1.5A  
1
Supply voltage, VDD  
1
Output voltage , VPP  
Logic input levels1  
Ground current2  
Continuous total power dissipation3  
Operating temperature range  
Storage temperature range  
1200mW  
-40°C to +85°C  
-65°C to +150°C  
80  
1
Lead temperature 1.6mm from  
case for 10 seconds  
80-Lead PQFP (PG)  
260°C  
(top view)  
Absolute Maximum Ratings are those values beyond which damage to the  
device may occur. Functional operation under these conditions is not implied.  
Continuous operation of the device at the absolute rating level may affect  
device reliability.  
Product Marking  
L = Lot Number  
HV57009PG  
LLLLLLLLLLL  
YYWW  
YY = Year Sealed  
WW = Week Sealed  
C = Country of Origin  
A = Assembler ID  
Notes:  
1. All voltages are referenced to VSS  
2. Limited by the total dissipated in the package.  
3. For operation above 25°C ambiant derate linearly to maximum  
operating temperature at 20mW/°C.  
CCCCCCCCC AAA  
= “Green” Packaging  
80-Lead PQFP (PG)  
Recommended Operating Conditions  
Symbol  
Parameter  
Min  
4.5  
Max  
5.5  
VDD  
-
Units  
VDD  
Logic supply voltage  
HV output off voltage  
High-level input voltage  
Low-level input voltage  
V
V
V
V
HVOUT  
VIH  
-85  
VDD - 1.2V  
0
VIL  
1.2  
8.0  
4.5  
+85  
fCLK  
TA  
Clock frequency per register  
Operating free-air temperature  
DC  
-40  
MHz  
°C  
Notes:  
Power-up sequence should be the following:  
1. Apply ground  
2. Apply VDD  
3. Set all inputs (DIN, CLK, LE) to a known state  
Power-down sequence should be the reverse of the above  
2