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HV5408PJ-B-G 参数 Datasheet PDF下载

HV5408PJ-B-G图片预览
型号: HV5408PJ-B-G
PDF下载: 下载PDF文件 查看货源
内容描述: [AC Plasma Driver, 32-Segment, CMOS, PQCC44, 0.653 X 0.653 INCH, 0.180 INCH HEIGHT, 0.050 INCH PITCH, GREEN, PLASTIC, MS-018AC, LCC-44]
分类和应用: 高压
文件页数/大小: 6 页 / 457 K
品牌: SUPERTEX [ Supertex, Inc ]
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HV5308/HV5408  
Electrical Characteristics (VPP = 60V, VDD = 12V, TA =25°C)  
DC Characteristics  
Symbol  
Parameter  
Min  
Max  
0.5  
100  
15  
Units  
mA  
Conditions  
IPP  
VPP Supply Current  
HVoutputs HIGH to LOW  
All inputs = VDD or GND  
IDDQ  
IDD  
IDD Supply Current (Quiescent)  
IDD Supply Current (Operating)  
µA  
mA  
VDD = VDD max,  
fCLK = 8 MHz  
V
OH (Data)  
OL (Data)  
Shift Register Output Voltage  
Shift Register Output Voltage  
Current Leakage, any input  
Current Leakage, any input  
HV Output Clamp Diode Voltage  
HV Output when Sourcing  
HV Output when Sinking  
10.5  
V
V
IO = 100µA  
V
1
1
IO = 100µA  
IIH  
µA  
µA  
V
VIN = VDD  
IIL  
-1  
VIN = 0  
VOC  
VOH  
VOL  
VOH  
VOL  
-1.5  
IOL = -100mA  
52  
52  
V
IOH = -20mA, -40 to 85°C  
IOL = 20mA, -40 to 85°C  
IOH = -15mA, -55 to 125°C  
IOL = 15mA, -55 to 125°C  
8
8
V
HV Output when Sourcing  
HV Output when Sinking  
V
V
AC Characteristics  
Symbol  
Parameter  
Min  
Max  
Units  
MHz  
ns  
Conditions  
fCLK  
Clock Frequency  
8
t
WL or tWH  
tSU  
tH  
DLH (Data)  
Clock width, HIGH or LOW  
Setup time before CLK rises  
Hold time after CLK rises  
Data Output Delay after L to H CLK  
Data Output Delay after H to L CLK  
LE Delay after L to H CLK  
Width of LE Pulse  
62  
25  
10  
ns  
ns  
t
110  
110  
ns  
CL = 15pF  
CL = 15pF  
tDHL (Data)  
tDLE  
ns  
50  
50  
50  
ns  
tWLE  
ns  
tSLE  
LE Setup Time before L to H CLK  
Delay from LE to HVOUT, L to H  
Delay from LE to HVOUT, H to L  
ns  
tON  
500  
500  
ns  
tOFF  
ns  
Recommended Operating Conditions  
(over -40 to 85°C for plastic and -55°C to 125°C for ceramic)  
Symbol  
VDD  
Parameter  
Min  
10.8  
8.0  
VDD-2  
0
Max  
13.2  
80  
Units  
Logic Voltage Supply  
High Voltage Supply  
Input HIGH Voltage  
Input LOW Voltage  
Clock Frequency  
V
V
VPP  
VIH  
VDD  
2
V
VIL  
V
fCLK  
0
8
MHz  
Note:  
Power-up sequence should be the following:  
1. Connect ground.  
2. Apply VDD  
3. Set all inputs (Data, CLK, LE, etc.) to a known state.  
4. Apply VPP  
.
.
5. The VPP should not fall below VDD or float during operation.  
Power-down sequence should be the reverse of the above.  
2
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