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HV5308PG 参数 Datasheet PDF下载

HV5308PG图片预览
型号: HV5308PG
PDF下载: 下载PDF文件 查看货源
内容描述: 32通道串行到并行转换高压推挽输出 [32-Channel Serial To Parallel Converter With High Voltage Push-Pull Outputs]
分类和应用: 接口集成电路高压驱动
文件页数/大小: 6 页 / 461 K
品牌: SUPERTEX [ Supertex, Inc ]
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HV5308/HV5408
Electrical Characteristics
(V
PP
= 60V, V
DD
= 12V, T
A
=25°C)
DC Characteristics
Symbol
I
PP
I
DDQ
I
DD
V
OH
(Data)
V
OL
(Data)
I
IH
I
IL
V
OC
V
OH
V
OL
V
OH
V
OL
Parameter
V
PP
Supply Current
I
DD
Supply Current (Quiescent)
I
DD
Supply Current (Operating)
Shift Register Output Voltage
Shift Register Output Voltage
Current Leakage, any input
Current Leakage, any input
HV Output Clamp Diode Voltage
HV Output when Sourcing
HV Output when Sinking
HV Output when Sourcing
HV Output when Sinking
52
8
52
8
10.5
1
1
-1
-1.5
Min
Max
0.5
100
15
Units
mA
µA
mA
V
V
µA
µA
V
V
V
V
V
Conditions
HVoutputs HIGH to LOW
All inputs = V
DD
or GND
V
DD
= V
DD
max,
f
CLK
= 8 MHz
I
O
= 100µA
I
O
= 100µA
V
IN
= V
DD
V
IN
= 0
I
OL
= -100mA
I
OH
= -20mA, -40 to 85°C
I
OL
= 20mA, -40 to 85°C
I
OH
= -15mA, -55 to 125°C
I
OL
= 15mA, -55 to 125°C
AC Characteristics
Symbol
f
CLK
t
WL
or t
WH
t
SU
t
H
t
DLH
(Data)
t
DHL
(Data)
t
DLE
t
WLE
t
SLE
t
ON
t
OFF
Parameter
Clock Frequency
Clock width, HIGH or LOW
Setup time before CLK rises
Hold time after CLK rises
Data Output Delay after L to H CLK
Data Output Delay after H to L CLK
LE Delay after L to H CLK
Width of LE Pulse
LE Setup Time before L to H CLK
Delay from LE to HV
OUT
, L to H
Delay from LE to HV
OUT
, H to L
50
50
50
500
500
62
25
10
110
110
Min
Max
8
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
L
= 15pF
C
L
= 15pF
Conditions
Recommended Operating Conditions
(over -40 to 85°C for plastic and -55°C to 125°C for ceramic)
Symbol
V
DD
V
PP
V
IH
V
IL
f
CLK
Parameter
Logic Voltage Supply
High Voltage Supply
Input HIGH Voltage
Input LOW Voltage
Clock Frequency
Min
10.8
8.0
V
DD
-2
0
0
Max
13.2
80
V
DD
2
8
Units
V
V
V
V
MHz
Note:
Power-up sequence should be the following:
1. Connect ground.
2. Apply V
DD
.
3. Set all inputs (Data, CLK, LE, etc.) to a known state.
4. Apply V
PP
.
5. The V
PP
should not fall below V
DD
or float during operation.
Power-down sequence should be the reverse of the above.
2