HV528
Functional Block Diagram
VDD
DIN
Logic
Level
Translator
HV
OUT
1
CLK
16-bit
Shift
Register
GND
HVGND
16-bit
Latch
Level
Translator
Logic
HV
OUT
16
HVGND
DOUT
GND
HVGND
GND
LE
POL
Level
Translator
&
Buffer
HVGND
BP
Function Table
Inputs
Function
DIN
H OR L
X
X
X
Store data in latches
X
L
H
X
X
CLK
↑
L
L
X
X
↑
↑
X
X
LE
H
L
L
H
H
L
L
H
H
POL
X
H
L
H
L
H
H
L
H
Shift Reg
1 2...16
H or L
*
*
●
●
L
H
●
●
●...●
*
*
●
●
L
H
●
●
Outputs
HV Outputs
1 2...16
●
●...●
*..........*
*..........*
(b)
●...●
●...●
(b)
●...●
●...●
●...●
(b)
●...●
BP
X
L
H
L
H
L
L
H
L
DOUT
●
●
●
●
●
●
●
X
X
Load S/R
Transfer data in
latch
*..........*
*..........*
●...●
●...●
●...●
●...●
●...●
●...●
Transparent mode
Invert mode
Notes:
H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition
● = dependent on previous stage’s state before the last CLK or last LE low
*
= data at the last CLK ↑
(b) = bar over all symbols
6
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