HV509
Ordering Information
Package Options
Device
HV509
32-Lead QFN
5x5mm body, 1.0mm height (max), 0.50 pitch
Pin Configuration
HV509K6-G
-G indicates package is RoHS compliant (‘Green’)
32
1
32-Lead QFN
(top view)
Absolute Maximum Ratings
Parameter
Logic supply, V
DD
High voltage supply, V
PP
Translator supply voltage, V
BIAS
Logic input levels
Operating junction temperature
Storage temperature range
Value
-0.5V to 7.0V
215V
-0.5V to 7.0V
-0.5V to V
DD
+ 0.5V
-40°C to +125°C
-65°C to +150°C
Pads are at the bottom of the package.
Exposed heat slug is at V
PP
potential.
Product Marking
HV509
LLLLLL
YYWW
AAACCC
L = Lot Number
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
= “Green” Packaging
32-Lead QFN
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
Operating Supply Voltages and Conditions
Symbol
V
DD
V
BIAS
V
PP
V
IH
V
IL
T
A
Parameter
Logic supply voltage
Level translator supply voltage
Positive high voltage supply
High-level input voltage
Low-level input voltage
Operating temperature
Min
2.0
2.6
50
0.9V
DD
0
0
Typ
3.0
-
-
-
-
-
Max
5.5
6.6
200
V
DD
0.1V
DD
+70
Units
V
V
V
V
V
°C
Conditions
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Notes:
(1) External ground noise reduction circuit will be provided by design upon characterization.
(2) Power-up sequence should be the following*:
1. Apply ground
2. Apply V
DD
3. Set all inputs (D
IN
, CLK, LE , POL) to a known state
4. Apply V
BIAS
5. Apply V
PP
(3) Power-down sequence should be the reverse of the above
*This power up sequence requires an external high voltage diode between VDD and VPP. Without the diode, power up VPP to a VDD level first to
bias the silicon substrate. After all other signals are powered, finish raising the V
PP
to its final level.
2
SUPERTEX [ Supertex, Inc ]
