HV506
Functional Block Diagram
VDD
OE
POL
LVDD
Output
DRIOA
HVOUT1
CLK
S/R
DIR
Output
HVOUT2
DRIOB
Output
HVOUT40
LVSS
VSS
DP
DN
Function Table
I/O Relations
CLK
O/P HIGH
O/P OFF
O/P LOW
O/P OFF
X
X
X
X
DIR
X
X
X
X
Inputs
S/R Data
H
L
H
X
POL
H
X
L
X
OE
L
L
L
H
HV Outputs
H
HIGH-Z
L
All O/P HIGH-Z
Note:
H = logic high level, L = logic low level, X = irrelevant
Output Sequence Operation Table
DIR
L
H
Data Reset In Data Reset Out
DR
IOB
DR
IOA
DR
IOA1
DR
IOB2
HV
OUT
# Sequence
40
→
1
1
→
40
Direction
3
Notes:
1. DR
IOA
is DR
IOB
delayed by 40 clock pulses.
2. DR
IOB
is DR
IOA
delayed by 40 clock pulses.
3. Reference to chip layout drawing.
6