HV4937
Functional Block Diagram
V
SS
Output Enable
Latch Enable
Data Input
HV
OUT
1
Clock
HV
OUT
2
64 bit
Static Shift
Register
64 Latches
•
•
•
60 Additional
Outputs
•
•
•
HV
OUT
63
DIR
HV
OUT
64
Data Out
Function Table
Inputs
Function
All off
Load S/R
Data
X
H or L
H or L
Load Latch
Output Enable
Transparent Latch
Mode
H or L
X
H
L
CLK
X
↓
↓
↓
H or L
↓
↓
LE
X
L
L
H
H
H
H
OE
L
L
L
L
H
H
H
DIR
X
H
L
X
X
X
X
Shift Reg
1 2
…
64
*…*
H or L…Qn
→
Qn+1
H or L…Qn
→
Qn-1
H or L…*
H or L…*
H…*
L
…*
Outputs
Latch
HV
OUT
1 2
…
64 1 2
…
64
*…*
*…*
*…*
H or L…*
H or L…*
H…*
L…*
H…H
H…H
H…H
H…H
L or H…*
L
…*
H…*
D
OUT
*
*
*
*
*
*
*
Notes:
X = Don’t care
* = Dependent on previous stage’s state before the last CLK : High to low transition.
↓
= -5V to V
SS
transition
H = V
DD
L = V
SS
12-32